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| Number | Title | Issue Date |
| 7275189 | Memory module and method for operating a memory module in a data memory system Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality for conditioning data signals that are transferred to the memory module and output from the memory modul... | 09/25/2007 |
| 7272773 | Cache directory array recovery mechanism to support special ECC stuck bit matrix A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a pl... | 09/18/2007 |
| 7272666 | Storage management device A storage management device includes a plurality of I/O processing modules for accessing units of storage by specifying an address and a time. The I/O processing modules receive I/O requests, classify I/O requests, and extract I/O control information associated with... | 09/18/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7272757 | Method for testing a memory chip and test arrangement A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correct... | 09/18/2007 |
| 7272775 | Memory circuit comprising an error correcting code A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error cor... | 09/18/2007 |
| 7272772 | Data recording method, recording medium and reproduction apparatus A recording medium is provided for storing a data stream containing first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting co... | 09/18/2007 |
| 7269759 | Data processing apparatus and method for handling corrupted data values The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within t... | 09/11/2007 |
| 7266759 | Semiconductor integrated circuit device and error checking and correcting method thereof A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time durin... | 09/04/2007 |
| 7266026 | Symbol frequency leveling in a storage system Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes ge... | 09/04/2007 |
| 7266724 | Apparatus and method for interruption of read and write operation and program storage medium for storing read and write procedure program A method and an apparatus for performing high-quality read and write operations through a simple operation without being affected by an interruption even when the interruption has occurred in the course of a read/write operation between information storage media. Wh... | 09/04/2007 |
| 7266732 | MRAM with controller A memory card comprising an magnetic random access memory (MRAM) array that comprises a plurality of magnetic memory cells and a controller coupled to the MRAM array. The controller is configured to communicate with a host device, and the controller is configured pe... | 09/04/2007 |
| 7266735 | Semiconductor device having ECC circuit A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together ... | 09/04/2007 |
| 7263649 | Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule gen... | 08/28/2007 |
| 7263724 | Unauthorized usage monitoring system for image forming apparatus When a digital copier is used, for monochrome images, image data is stored into a storage in association with user ID codes at a 5% possibility while for color images, image data is stored in association with user ID codes at possibilities ranging from 0 to 50% depe... | 08/28/2007 |
| 7263383 | Apparatus and a method for extending phone book records of a subscriber identification module (SIM) card An apparatus for extending “phone book” records of a subscriber identification module (SIM) card comprising a detecting module for accessing a subscriber identification code (SIC) of the SIM card and a memory is provided. A storage window marked by the SIC is de... | 08/28/2007 |
| 7263648 | Apparatus and method for accommodating loss of signal A memory control system for a network that broadcasts to multiple terminals content data including music, video and the like, and also including commercial advertisements. A memory in the terminal unit stores content data that is played upon a loss of signal from th... | 08/28/2007 |
| 7260691 | Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routi... | 08/21/2007 |
| 7260848 | Hardened extensible firmware framework A method for hardening an extensible firmware framework and system in which the framework is implemented. In accordance with the method, a resource access policy that defines rules to allow or disallow access to designated system resources, such as memory and I/O, i... | 08/21/2007 |
| 7256989 | Removable hard disk housing assembly The removable hard disk housing assembly includes a housing substrate, a hard disk supporting frame, a rotatable handle, a supporting piece, two plates-liked elements and two springs. The hard disk supporting frame is connected with the housing substrate to support ... | 08/14/2007 |
| 7257762 | Memory interface with write buffer and encoder A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer alon... | 08/14/2007 |
| 7257761 | Method for preventing read errors in optical disc drive A method for improving data accuracy and data flow of a disc servo system to read data on a disk. First of all, a read mode of the disc servo system is determined. If the read mode is an audio/video play mode, a first read procedure to read the data on the disk is e... | 08/14/2007 |
| 7257129 | Memory architecture with multiple serial communications ports A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area netwo... | 08/14/2007 |
| 7257672 | Error protection for lookup operations performed on ternary content-addressable memory entries Lookup operations are performed on ternary content-addressable memory (TCAM) entries, with error protection provided. Groups of TCAM entries are programmed such that each of its entries differ by more than a predetermined calculated count of ones distance of k bits,... | 08/14/2007 |
| 7257750 | Self-verification of configuration memory in programmable logic devices In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the maske... | 08/14/2007 |
| 7254667 | Data transfer between an external data source and a memory associated with a data processor A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 | 08/07/2007 |
| 7254060 | Nonvolatile semiconductor memory device The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The d... | 08/07/2007 |
| 7254748 | Error correcting content addressable memory A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entri... | 08/07/2007 |
| 7254768 | Memory command unit throttle and error recovery A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network ... | 08/07/2007 |
| 7251744 | Memory check architecture and method for a multiprocessor computer system Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wh... | 07/31/2007 |
| 7251767 | Method for correcting errors in a packet-oriented data transmission Descriptors are used, which combine the code words of a transmission block of the same correctability into a subset, and which describe the size of the subset as well as the difference in the correctability of the previously concerned subset. ... | 07/31/2007 |
| 7251773 | Beacon to visually locate memory module One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state in the memory module is activated due to receipt of the electronic com... | 07/31/2007 |
| 7249308 | Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls A system for testing logical partitioning. In a preferred embodiment, an I/O adapter is configured to break partitioning rules, for example, to attempt to access addresses outside a valid address range. Software is used to check for expected errors at expected addre... | 07/24/2007 |
| 7249244 | Data processing system The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (13), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the s... | 07/24/2007 |
| 7246300 | Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through ... | 07/17/2007 |
| 7243277 | Method of combining multilevel memory cells for an error correction scheme A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without in... | 07/10/2007 |
| 7243290 | Data encoding for fast CAM and TCAM access times A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an encoded CAM or TCAM word such that a one-bit mismatch between a compa... | 07/10/2007 |
| 7240254 | Multiple power levels for a chip within a multi-chip semiconductor package A semiconductor memory chip is provided for packaging along with a system chip in a single semiconductor package having a plurality of external connectors. The memory chip includes a memory storage array for storing data. A plurality of data buffers is provided for ... | 07/03/2007 |
| 7240144 | Arbitration of data transfer requests A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portio... | 07/03/2007 |
| 7240218 | Method of using a mask programmed key to securely configure a field programmable gate array A field programmable gate array has security configuration features to prevent monitoring of the configuration data for the field programmable gate array. The configuration data is encrypted by a security circuit of the field programmable gate array using a security... | 07/03/2007 |
