Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 4942578 | Buffer control method and apparatus A multiprocessor stores in a directory a validity bit for a line of a cache, history of updating and information relating to equality of data between processors. A portion of an error in the information bits in an IC chip is recovered by a circuit for det... | 07/17/1990 |
| 4920537 | Method and apparatus for non-intrusive bit error rate testing This invention comprises a method and apparatus for determining the bit error rate (BER) between two points of a digital communications circuit carrying an arbitrary data stream. Block check codes calculated at one point are compared with those calculated... | 04/24/1990 |
| 4918695 | Failure detection for partial write operations for memories A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including ... | 04/17/1990 |
| 4901318 | Address generating circuit An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The reading address is obtainable based on a formula RDA=H+2L+p, whe... | 02/13/1990 |
| 4899342 | Method and apparatus for operating multi-unit array of memories A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and ... | 02/06/1990 |
| 4887268 | Error checking apparatus An error checking apparatus includes first and second switching circuits arranged at input and output ports of a data processing circuit for processing data constituted by a plurality of parallel bits to be transferred through a plurality of transmission ... | 12/12/1989 |
| 4866719 | System and method for performing error correction on still frame audio tape format video signals A system and method for performing error correction on an SFAT format video signal which has been encoded using an error correction code ECC2, and generating a video signal reconstructed from the error-corrected input signal. The error code preferably is ... | 09/12/1989 |
| 4862462 | Memory systems and related error detection and correction apparatus Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing S... | 08/29/1989 |
| 4858235 | Information storage apparatus In an information storage apparatus having an error-correcting code, wherein digital information and check symbols are stored in groups of codewords which are divided into blocks of equal size and a synchronization field for data synchronization is added ... | 08/15/1989 |
| 4852100 | Error detection and correction scheme for main storage unit The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and... | 07/25/1989 |
| 4827478 | Data integrity checking with fault tolerance Fault tolerant apparatus for generating error correcting code and, simultaneous therewith, checking the correctness of the generation, for blocks of data with which the error correcting code is associated and transmitted to a storage medium. The apparatus... | 05/02/1989 |
| 4788685 | Apparatus for recording and reproducing data A recording and reproducing apparatus comprising a memory for storing input data to be recorded in units of a predetermined quantity, a first address control means for generating only sequential memory addresses, a second address control means for generat... | 11/29/1988 |
| 4780809 | Apparatus for storing data with deferred uncorrectable error reporting The reporting of errors that are detected when data which contains an error is moved from a high speed buffer memory array to a main storage array is deferred so that the error checking and correcting logic associated with the main storage memory array wi... | 10/25/1988 |
| 4775979 | Error correction system An error correction system for a memory device of the type in which a data of plurality of bits is stored in a storage in the form of a coded word having as an end portion thereof a plurality of check bits produced in accordance with a predetermined parit... | 10/04/1988 |
| 4761783 | Apparatus and method for reporting occurrences of errors in signals stored in a data processor The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals; second circuitry for storing the multiple digital first sign... | 08/02/1988 |
| 4727547 | Method and apparatus for decoding Method and apparatus for transforming a first sequence of digital data and correction words having a first ordering thereof wherein blocks of data and correction words in the first ordering are formed out of the first sequence Data and correction words ar... | 02/23/1988 |
| 4694456 | Information signal reproducing apparatus An information signal reproducing apparatus comprises a memory for storing encoded digital data and error correction data, and a decoder for decoding the digital data, producing decoded digital data organized in blocks, and delivering the decoded digital ... | 09/15/1987 |
| 4672613 | System for transferring digital data between a host device and a recording medium In a system for transferring data between a host device and a target recording medium, a buffer interface control unit includes a host direct memory access (DMA) unit for transferring data from the host unit to a buffer memory. The host DMA unit accesses ... | 06/09/1987 |
| 4651321 | Apparatus for reducing storage necessary for error correction and detection in data processing machines Present invention presents a novel mechanism for reducing the amount of storage space necessary to perform error checking and correcting in a storage unit of a data processing machine by utilizing the information present in the parity checking portion of ... | 03/17/1987 |
| 4646312 | Error detection and correction system An error detection and correction apparatus including a transmission bus for transmitting multi-bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code tech... | 02/24/1987 |
| 4641310 | Data processing system in which unreliable words in the memory are replaced by an unreliability indicator A data processing system comprising a memory receives data in the form of data blocks. Such a data block contains at least one data word and check bits. On the basis of the check bits it is vertified whether the data block contains reliable or unreliable ... | 02/03/1987 |
| 4633471 | Error detection and correction in an optical storage system A self-checking shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte o... | 12/30/1986 |
| 4621364 | Circuit arrangement for recording the addresses of storage cells with erroneous content To record the address of a storage cell that has contents that are erroneous with respect to the coding, a memory configuration, connected by means of a bus line system with a central control unit, is equipped with a register in the recording cells of whi... | 11/04/1986 |
| 4604751 | Error logging memory system for avoiding miscorrection of triple errors Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a... | 08/05/1986 |
| 4569052 | Coset code generator for computer memory protection An apparatus for protecting computer memory utilizes a parity matrix to generate an n-k check bit signal of an extended linear (n,k,4) code from a k data bit signal. Exclusive-OR gates add the n-k check bit signal to an n-k tag bit signal selected from a ... | 02/04/1986 |
| 4562576 | Data storage apparatus Data storage apparatus consisting of an array of RAM chips, with Hamming code checking for detecting double-bit errors. Address signals are fanned-out to the chips by way of driver circuits. Each driver circuit distributes an address bit to only two colum... | 12/31/1985 |
| 4521872 | Instruction storage An instruction storage for storing microinstructions or macroinstructions is disclosed. Each instruction word includes error check and correction bits to enable error correction when an error is detected, and a plurality of instructions are assembled from... | 06/04/1985 |
| 4506362 | Systematic memory error detection and correction apparatus and method A systematic data memory error detection and correction apparatus periodically reads data from each addressable memory location, determines the presence or absence of an error in the addressed data memory location and, if an error is detected, corrects th... | 03/19/1985 |
| 4464752 | Multiple event hardened core memory A computer system is provided for reconstructing a word, which is altered during cycling of the computer memory when a nuclear event occurs. The computer system includes a nuclear event detector, a circuit for setting flags in response to the detection of... | 08/07/1984 |
| 4455655 | Real time fault tolerant error correction mechanism The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as a data transfer circuit between a disc memory and a processing unit. It operates in two modes: as an encoding system and error det... | 06/19/1984 |
| 4410988 | Out of cycle error correction apparatus This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system. The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the ... | 10/18/1983 |
| 4404673 | Error correcting network An error correcting network adapted for encoding and decoding data transferred to and from a bubble memory has parallel linear encoder/decoder circuits. An error syndrome generated in response to a parity error in an initial read operation is used by one ... | 09/13/1983 |
| 4388684 | Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals t... | 06/14/1983 |
| 4384353 | Method and means for internal error check in a digital memory A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. Whe... | 05/17/1983 |
| 4371949 | Time-shared, multi-phase memory accessing system having automatically updatable error logging means Automatically updatable error logging means incorporated in a multi-phase, bit addressable, variable field memory system. The memory system is partitioned into a plurality of individually addressable memory stacks and employs time-shared accessing of the ... | 02/01/1983 |
| 4363125 | Memory readback check method and apparatus A high speed readback check of data transferred to a cyclic memory before the data source is lost. The cyclic memory is organized into a number of data blocks, each interleaved with or simultaneously accessible with the other data blocks. Thus, a long dat... | 12/07/1982 |
| 4335458 | Memory incorporating error detection and correction A memory in which each word location for a user word not only contains the bit locations for the actual data but also one parity bit for the parity over the entire word location and one correction bit. A fixed number of word locations are grouped to form ... | 06/15/1982 |
| 4282551 | PCM Recording and reproducing apparatus When error detection codes are added to a sampled signal word which is a digital version of audio information and a control signal which is a digital version of system control information to construct a data frame and a control signal frame, respectively,... | 08/04/1981 |
| 4244049 | Method and apparatus for enhancing I/O transfers in a named data processing system In a named data processing system, user ownership and verfication of data records is secured by assigning an unique record name to each data record, providing error checking covering both the data record and its associated record name, storing the data re... | 01/06/1981 |
| 4225959 | Tri-state bussing system This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system. The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the ... | 09/30/1980 |
