Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 7197605 | Allocating cache lines Allocating cache lines includes incurring a cache write miss and, after incurring the cache write miss, writing data having a memory address to a cache line that does not include data at the memory address and that includes only invalid data. ... | 03/27/2007 |
| 7197669 | Method and circuit for command integrity checking (CIC) in a graphics controller A fault tolerant graphics controller that generates error codes for graphics commands and checks the error codes before the graphics controller executes the command. The error code generator may be configured to detect and correct errors or to just detect errors. If... | 03/27/2007 |
| 7191379 | Magnetic memory with error correction coding Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, prov... | 03/13/2007 |
| 7191257 | System and method for real-time processing of nondeterministic captured data events A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a ... | 03/13/2007 |
| 7187709 | High speed configurable transceiver architecture One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable ... | 03/06/2007 |
| 7188299 | Data-recording/reproduction apparatus and data-recording/reproduction method In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error c... | 03/06/2007 |
| 7184352 | Memory system and method using ECC to achieve low power refresh Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndr... | 02/27/2007 |
| 7185266 | Network interface device for error detection using partial CRCS of variable length message portions A device and method are disclosed for calculating a CRC on a message or block of data that has been divided into portions, by calculating a partial CRC corresponding to each of the portions and then combining the partial CRCs. The device and method are operable for ... | 02/27/2007 |
| 7181672 | Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices A technique for coalesced Power Loss Recovery PLR status bits in an Error Correction Code ECC enabled flash memory. ... | 02/20/2007 |
| 7181075 | Multi-level encoding/decoding apparatus A multi-level image encoding/decoding apparatus, which performs bit modeling processing on coefficients, which are the result of wavelet transform of a multi-level image read out from a transform coefficient storage memory, by accessing a significance information me... | 02/20/2007 |
| 7181636 | Method of ensuring synchronous presentation of additional data with audio data recorded on a rewritable recording medium A recording medium and a method and apparatus for managing data are provided. The method includes recording additional data in a data file separate from a file containing main data and recording navigation information that links the main data and the additional data... | 02/20/2007 |
| 7181645 | Method and apparatus for storing main data with two checkup data An electronic control unit has a microcomputer and a backup RAM, which stores its data irrespective of ON/OFF of an engine ignition switch. The backup RAM stores a main data in its storage area, and two checkup data in its storage areas, respectively. The two checku... | 02/20/2007 |
| 7178087 | Read-only record carrier with recordable area in subcode channel A method of providing a read-only record carrier on which user data can be recorded at predetermined recordable positions of subcode frames of a subcode channel after mastering of said record carrier, includes the steps of setting the subcode symbols at said predete... | 02/13/2007 |
| 7177975 | Card system with erase tagging hierarchy and group based write protection A low cost data storage and communication system is disclosed. The low cost data storage and communication system has a host and at least one card connected to the host. A voltage negotiator located in the system for determining a common operating voltage range that... | 02/13/2007 |
| 7177593 | Estimating communication quality A method for estimating quality of communications between a transmitter and a receiver over a communications link operable to carry data in at least one of a plurality of different compressed forms, the method comprising: detecting an error rate of the communication... | 02/13/2007 |
| 7174502 | Synchronization error detection circuit Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to the pulse rate, selecting the number generated when each transition ... | 02/06/2007 |
| 7173863 | Flash controller cache architecture A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Re... | 02/06/2007 |
| 7171606 | Software download control system, apparatus and method A system and method for downloading software updates for receivers of broadcast content data distribution has multiple memories for storing the updated version of code as well as a backup copy of the prior version of code. Code is replaced with an updated version wh... | 01/30/2007 |
| 7171605 | Check bit free error correction for sleep mode data retention A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding occurs at the time of entering the sleep mode and ECC decoding for error ... | 01/30/2007 |
| 7171599 | Field programmable device A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circui... | 01/30/2007 |
| 7167886 | Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 A method for constructing a logic circuit for inversion in finite field GF(2m) is described, where m=nk, and k, n are coprime numbers, using bases in subfields GF(2n) and GF(2k). The method may be applied to error correction codes, i... | 01/23/2007 |
| 7167404 | Method and device for testing configuration memory cells in programmable logic devices (PLDS) A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage devi... | 01/23/2007 |
| 7167114 | Memory efficient interleaving A method and system using a single interleaver at a either a receiving device or a transmitting device where a first symbol set is read from the single interleaver and concurrently with a second symbol set is written to the single interleaver, and a controller that ... | 01/23/2007 |
| 7167524 | Method of inserting sync data in modulated data and recording medium containing the sync data The present invention relates to a method of inserting sync patterns of different lengths in modulated data, and a recording medium having sync patterns produced by the method. The sector sync and the frame sync pattern to be inserted in modulated data in accordance... | 01/23/2007 |
| 7165206 | SRAM-compatible memory for correcting invalid output data using parity and method of driving the same Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respe... | 01/16/2007 |
| 7165205 | Method and apparatus for encoding and decoding data A method for interlacing columns of different weights is proposed for a parity-check matrix H that results in good performing LDPC codes shortened or unshortened. Matrix H comprises a section H1 and a section H2, and wherein H1 has a... | 01/16/2007 |
| 7162681 | Information reproducing apparatus, method of correcting reproducing program, and information recording medium An information reproducing apparatus, in which a disk having correction data recorded thereon is placed, acquires region information indicative of a region corresponding to the correction data after load processing is performed by a ROM loader. Then, under the contr... | 01/09/2007 |
| 7162661 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 01/09/2007 |
| 7161867 | Semiconductor memory device In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first ... | 01/09/2007 |
| 7159165 | Optical recording medium, data recording or reproducing apparatus and data recording or reproducing method used by the data recording or reproducing apparatus An optical recording medium, a data recording or reproducing apparatus, and a data recording or reproducing method used by the data recording or reproducing apparatus. In a method of recording data on an optical disc, each of a plurality of error correction code (EC... | 01/02/2007 |
| 7159164 | Method and apparatus for recovery of particular bits of a frame A method and an apparatus for recovery of particular bits in a frame are disclosed. An origination station forms a frame structure with groups of information bits of different importance. All the information bits are then protected by an outer quality metric. Additi... | 01/02/2007 |
| 7159141 | Repairable block redundancy scheme A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch ... | 01/02/2007 |
| 7159139 | Digital data storage subsystem including directory for efficiently providing formatting information for stopped records and utilization of a check value for verifying that a record is from a particular storage location A digital data storage system in the form of a mass storage subsystem in which information is stored on one or more disk storage units, with a storage element constituting a track on a disk storage device and each track storing a plurality of records. Each track in ... | 01/02/2007 |
| 7159069 | Simultaneous external read operation during internal programming in a flash memory device A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and... | 01/02/2007 |
| 7154835 | Digital signal processing method, data recording and reproducing apparatus, and data recording medium that are resistant to burst errors With two consecutive product-coded ECC blocks, EB1 and EB2, as a set, the rth row of first ECB block EB1 is followed by the rth row of second ECC block EB2 in such a way that the first row of first ECC block EB1 is followed by the ... | 12/26/2006 |
| 7152187 | Low-power SRAM E-fuse repair methodology A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memorie... | 12/19/2006 |
| 7149950 | Assisted memory device for reading and writing single and multiple units of data A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the ... | 12/12/2006 |
| 7149949 | Method for error correction decoding in a magnetoresistive solid-state storage device A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells in a test row are used to predict failures amongst a set of cells of interest storing a block of ECC ... | 12/12/2006 |
| 7149948 | Manufacturing test for a fault tolerant magnetoresistive solid-state storage device A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suita... | 12/12/2006 |
| 7149947 | Method of and system for validating an error correction code and parity information associated with a data word A data processing system includes an input portion for receiving a digital word having N bits of data and M bits for error detection, a first error correction code generator for generating a first error correction code based on the N bits of data of the digital word... | 12/12/2006 |
