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| Number | Title | Issue Date |
| 5903580 | Fault simulator of creating a signal pattern for use in a fault inspection of a semiconductor integrated circuit A fault simulator comprises a storage for storing a truth table that is a fault model, a simulation executing unit for executing a simulation on the basis of a given signal pattern by the use of the truth table stored in the storage, a simulation result j... | 05/11/1999 |
| 5896401 | Fault simulator for digital circuitry A fault simulator for a digital combinational circuit implements a critical path tracing algorithm in reconfigurable hardware and comprises: a forward network capable of emulating the digital combinational circuit and having primary outputs; a second forw... | 04/20/1999 |
| 5859962 | Automated verification of digital design A system for verifying design of a digital system. A digital system, which receives input vectors and produces output vectors, is simulated. The invention generates a sequence of synthesized input vectors, and applies them to the simulated system. These i... | 01/12/1999 |
| 5831998 | Method of testcase optimization A new method of testcase optimization for generating testcases is provided which is both efficient and effective. A 2-level heuristic is employed. The method is iterative, and at each iteration, at the first level of the heuristic, a greedy algorithm is u... | 11/03/1998 |
| 5818850 | Speed coverage tool and method A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing si... | 10/06/1998 |
| 5815513 | Test pattern preparation system A test pattern preparation system for testing an LSI circuit, the system includes: a circuit data file for storing various circuit data; an old test pattern file for storing old test patterns; a test pattern preparation unit for performing a logic simulat... | 09/29/1998 |
| 5754454 | Method for determining functional equivalence between design models The present invention determines whether two design files have identical functionality by attempting to create a binary decision diagram (BDD) for corresponding verification output pairs(302). When the BDD creations are not successful for all evaluated ou... | 05/19/1998 |
| 5745501 | Apparatus and method for generating integrated circuit test patterns A method and apparatus for generating integrated circuit test patterns (218) to test a functionality of integrated circuits. Module test stimuli (202) for each module present in an integrated circuit (10) are generated and retained (102). The module test ... | 04/28/1998 |
| 5633813 | Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fa... | 05/27/1997 |
| 5594741 | Method for control of random test vector generation A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integra... | 01/14/1997 |
| 5583787 | Method and data processing system for determining electrical circuit path delays A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, ... | 12/10/1996 |
| 5566187 | Method for identifying untestable faults in logic circuits A method of identifying untestable faults in a logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be untestable if the selected circuit lead were unable to assume a logic 0 and which faults would b... | 10/15/1996 |
| 5557774 | Method for making test environmental programs Test environmental programs are prepared using the following steps: Upon application of H/W specification information containing information on the system architecture, a guidance is displayed based on the H/W specification information and the user is cau... | 09/17/1996 |
| 5546408 | Hierarchical pattern faults for describing logic circuit failure mechanisms A method and system (12) for defining and using a pattern fault file (15) having a static pattern fault and/or a dynamic pattern fault. A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propa... | 08/13/1996 |
| 5502729 | Method of testing for stuck-at fault in a synchronous circuit The time series test pattern is generated by applying a system clock to the synchronous circuit. By expanding the synchronous circuit into a plurality of combinational circuit. The internal input to the combinational circuit is changed without applying th... | 03/26/1996 |
| 5479414 | Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at th... | 12/26/1995 |
| 5446674 | Crosstalk verification device A crosstalk verification device for preventing cross talk of an LSI layout pattern. An error extracting portion (17) which, referring to the contents of a design rule file (12) and a crosstalk noise reference voltage storing portion (18), processes coordi... | 08/29/1995 |
| 5410548 | Test pattern fault equivalence A method for determining test pattern fault equivalence. The method comprises selecting a bridging fault (16) from a digital circuit, then determining a stuck-at fault (17) which guarantees detection of the bridging fault. Generation of a test vector (18)... | 04/25/1995 |
| 5390193 | Test pattern generation A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as ... | 02/14/1995 |
| 5377201 | Transitive closure based process for generating test vectors for VLSI circuit A process for generating a vector for testing a digital circuit for a given fault first creates a composite circuit including a fault-present version of the circuit and a fault-free version. An implication graph is developed for the composite circuit and ... | 12/27/1994 |
| 5377202 | Method and apparatus for limiting pin driver offset voltages A test equipment pin driver having a main output channel including a pulse forming circuit, a buffer and an output amplifier connected in series. The pulse forming circuit provides pulses that are timed to a data input signal, and the buffer passes the pu... | 12/27/1994 |
| 5363319 | Logic simulator A logic simulator having plural logic function sections for realizing a logic circuit, plural connection sections for connecting these logic function sections, a control section for constructing a logic simulation circuit by controlling these logic functi... | 11/08/1994 |
| 5345450 | Method of compressing and decompressing simulation data for generating a test program for testing a logic device A method for simulating a logic device is described wherein a sequence of input vectors to a computer simulation is reduced in order to save computational time and data storage requirements when the sequence includes a series of redundant input vectors ha... | 09/06/1994 |
| 5305328 | Method of test sequence generation An efficient method of generating test sequences for sequential circuits is disclosed. This method generates a test sequence for a combinational circuit which includes an object fault, examines memory elements where a resulting state (other than "don't ca... | 04/19/1994 |
| 4817093 | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creat... | 03/28/1989 |
| 4792951 | Apparatus and method of stimulating an equipment By using a combination memory, shift register, logic gates and buffers, a stimulator used in an automatic testing instrument is able to provide two data rates for stimulating different equipment under test. The fast data rate is obtained by serially shift... | 12/20/1988 |
| 4747102 | Method of controlling a logical simulation at a high speed In a method of controlling a logical simulation of a logic circuit comprising a plurality of logic elements which can be simulated by forming a shift register string, the logical simulation is carried out without serial shift operation of the shift regist... | 05/24/1988 |
| 4654851 | Multiple data path simulator A multiple data path simulator for use with a data generator having a clock output and a data output including a data delay with a predetermined number of outputs, a data multiplexer for selecting one of the outputs, a clock delay with a predetermined num... | 03/31/1987 |
| 4625332 | Programmable time varying attenuator A programmable time varying attenuator has a reprogrammable digital circuit or impressing an analog attenuation signal on a continuous wave noise signal. This signal is fed to the input of a receiver and since the digital circuitry can be reprogrammed with... | 11/25/1986 |
| 4622647 | System for the automatic testing of printed circuits The test system comprises a standard basic unit with a central unit, a read-only memory, a read/write memory for recording test programs transmitted from a bulk memory and interfaces; the basic unit is connected to the card to be tested via a specific uni... | 11/11/1986 |
| 4594692 | Seismic signal generator A system for testing seismic signal recording equipment wherein a test signal is generated which simulates the output of at least one seismic sensing device, and, thereafter, the test signal is applied to the seismic signal recording equipment. The test s... | 06/10/1986 |
| 4247941 | Simulator for bit and byte synchronized data network A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals... | 01/27/1981 |
| 4045736 | Method for composing electrical test patterns for testing AC parameters in integrated circuits A method is provided for generating electrical test patterns for testing functional AC parameters of integrated semiconductor circuits from the test patterns used for the more conventional testing of the DC parameters of such circuits. The AC parameters i... | 08/30/1977 |
