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| Number | Title | Issue Date |
| 8423849 | Device test data reuse for device simulation A method and system reuse data logs generated from testing of programmable devices in order to provide an input file of parameter values and settings for use in automatically configuring a device simulator. The programmable device testing process generates a data lo... | 04/16/2013 |
| 8418012 | Method of analyzing the safety of a device employing on target hardware description language based fault injection A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurabl... | 04/09/2013 |
| 8239717 | Logic verification apparatus To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a description of the logic fu... | 08/07/2012 |
| 8166362 | Fault detection method and apparatus for analog to digital converter circuits This invention relates to fault detection in electrical circuits, in particular it relates to fault detection for a plurality of adjacent input circuits. The invention provides a method and apparatus for detecting a control or communication fault on an analogue circ... | 04/24/2012 |
| 8145967 | System and method for verifying the receive path of an input/output component A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification l... | 03/27/2012 |
| 8117513 | Test method and test program of semiconductor logic circuit device In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unsp... | 02/14/2012 |
| 8103927 | Field mounting-type test apparatus and method for testing memory component or module in actual PC environment A field mounting-type test apparatus and method for enhancing competitiveness of a product by simulating various test conditions including a mounting environment for improving quality reliability of a memory device and by minimizing overall loss due to change in a m... | 01/24/2012 |
| 8086926 | Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals outputted from a plurality of scan chains in which a plurality of scan f... | 12/27/2011 |
| 8078928 | System and method for verifying the transmit path of an input/output component A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in ... | 12/13/2011 |
| 8006156 | Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual... | 08/23/2011 |
| 8001438 | Measuring bridge-fault coverage for test patterns within integrated circuits A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern ... | 08/16/2011 |
| 7984354 | Generating responses to patterns stimulating an electronic circuit with timing exception paths Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is ca... | 07/19/2011 |
| 7975198 | Test system and back annotation method A test system for performing a test of a device is provided that comprises a source file of a test plan that describes a program for performing a test, and one or more of elements that are formed in a unit that divides the source file into one or more blocks. The te... | 07/05/2011 |
| 7971120 | Method and apparatus for covering a multilayer process space during at-speed testing In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included... | 06/28/2011 |
| 7971119 | System and method for defect-based scan analysis A method for defect-based scan analysis comprises, determining a neighborhood net for a circuit node, injecting defects into the neighborhood net, modeling the defects with stuck-at-0 and stuck-at-1 fault models, generating and applying test patterns to the neighbor... | 06/28/2011 |
| 7913143 | Test quality evaluating and improving system for semiconductor integrated circuit and test quality evaluation and improvement method for semiconductor integrated circuit A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring ... | 03/22/2011 |
| 7913144 | Diagnostic device, diagnostic method, program, and recording medium Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element ... | 03/22/2011 |
| 7900112 | System and method for digital logic testing Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, wh... | 03/01/2011 |
| 7877659 | Memory model for functional verification of multi-processor systems Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes... | 01/25/2011 |
| 7865795 | Methods and apparatuses for generating a random sequence of commands for a semiconductor device Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated ... | 01/04/2011 |
| 7844873 | Fault location estimation system, fault location estimation method, and fault location estimation program for multiple faults in logic circuit A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking... | 11/30/2010 |
| 7831879 | Generating test coverage bin based on simulation result A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in th... | 11/09/2010 |
| 7818646 | Expectation based event verification A computer implemented method of verifying events generated by an agent includes detecting an input signal at an input of the agent, generating an expected output signal based at least in part on the input signal, detecting an output signal at an output of the agent... | 10/19/2010 |
| 7814387 | Circuit state scan-chain, data collection system and emulation and verification method The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and th... | 10/12/2010 |
| 7761765 | Automated root cause identification of logic controller failure A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic cont... | 07/20/2010 |
| 7721176 | Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The erro... | 05/18/2010 |
| 7676718 | Test circuit, method and apparatus for supporting circuit design, and computer product A first FF outputs a first signal. A second FF captures the first signal and outputs a second signal. Each of the first and the second FF has a clock terminal to capture a clock signal. A third FF captures the first signal in parallel with the second FF. The third F... | 03/09/2010 |
| 7673210 | Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test, includes: 1) for each of the plurality of faults, and for each of a plurality... | 03/02/2010 |
| 7644334 | Requirements-based test generation This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functional... | 01/05/2010 |
| 7640477 | Calibration system that can be utilized with a plurality of test system topologies A calibration system within a test system is disclosed. The calibration system may include a netlist, a path correction module, and a processor in signal communication with the path correction module. The netlist may include a list of electrical characteristics of c... | 12/29/2009 |
| 7610540 | Method for generating, from a test cube set, a generator configured to generate a test pattern Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan input... | 10/27/2009 |
| 7587649 | Testing of reconfigurable logic and interconnect sources Methods and systems for verifying the proper function of reconfigurable logic elements and reconfigurable interconnects are disclosed. Reconfigurable logic elements in an emulation integrated circuit are arranged such that one set of reconfigurable logic elements is... | 09/08/2009 |
| 7577889 | Method for detecting software errors and vulnerabilities The present embodiments provide methods for detecting errors and vulnerabilities in software without access to its source code. The method entails extracting functions from dynamically linked applications, determining error return codes and error numbers for the ext... | 08/18/2009 |
| 7559002 | Multi-thread parallel segment scan simulation of chip element performance A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring dat... | 07/07/2009 |
| 7555689 | Generating responses to patterns stimulating an electronic circuit with timing exception paths Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is cap... | 06/30/2009 |
| 7526703 | Method of test pattern generation in IC design simulation system The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merg... | 04/28/2009 |
| 7516383 | Method and apparatus for analyzing delay in circuit, and computer product An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit ... | 04/07/2009 |
| 7509552 | Multi-thread parallel segment scan simulation of chip element performance A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hard... | 03/24/2009 |
| 7493544 | Extending test sequences to accepting states State spaces are traversed to produce test cases, or test coverage. Test coverage is a test suite of sequences. Accepting states are defined. Expected costs are assigned to the test graph states. Strategies are created providing transitions to states with lower expe... | 02/17/2009 |
| 7487422 | Delayed processing of site-aware objects A device is tested using a system that includes automatic test equipment (ATE) and a computer. At the ATE, the testing includes receiving data from the device, and processing the data to obtain processed data. At the computer, the testing includes executing a comput... | 02/03/2009 |
