Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8145966 | Remote testing system and method A method and system of supporting and testing equipment distant from the support system are provided. The method includes the steps of forming a communications link between the equipment and the support system, using the support system to measure performance of the ... | 03/27/2012 |
| 7987442 | Fault dictionaries for integrated circuit yield and quality analysis methods and systems Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from... | 07/26/2011 |
| 7558999 | Learning based logic diagnosis A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device ... | 07/07/2009 |
| 7549099 | Testing apparatus and testing method A testing apparatus includes a logic comparing unit for comparing the output value with a predetermined expectation value; a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit; a... | 06/16/2009 |
| 7395478 | Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a f... | 07/01/2008 |
| 7353140 | Methods for monitoring and controlling boiler flames The current invention provides a method and apparatus, which uses symbol sequence techniques, temporal irreversibility, and/or cluster analysis to monitor the operating state of individual burner flames on a appropriate time scale. Both the method and apparatus of t... | 04/01/2008 |
| 7353442 | On-chip and at-speed tester for testing and characterization of different types of memories An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signa... | 04/01/2008 |
| 7325182 | Method and circuit arrangement for testing electrical modules The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The c... | 01/29/2008 |
| 7324352 | High capacity thin module system and method Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible c... | 01/29/2008 |
| 7324986 | Automatically facilitated support for complex electronic services Systems for an automatically facilitated support for complex electronic services include a plurality of databases having customer records and problem solving information to assist a user with problem resolution and a cycler module configured to access the databases.... | 01/29/2008 |
| 7302633 | LSI design system, logic correction support equipment, logic correction support method used therefor, and program therefor Logic correction support equipment supports logic correction of a logic circuit in LSI design for synthesizing a logic circuit from a register transfer level by logic synthesis. The logic correction support equipment finds a logic that was redundant before logic cor... | 11/27/2007 |
| 7293250 | Method of modeling physical layout of an electronic component in channel simulation A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generat... | 11/06/2007 |
| 7284159 | Fault injection method and system A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating ... | 10/16/2007 |
| 7251748 | System and method for determining a global ordering of events using timestamps A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global orderi... | 07/31/2007 |
| 7246290 | Determining the health of a desired node in a multi-level system A method and apparatus are provided for determining the health of a desired node in a multi-level system. The method includes defining a first fault model associated with a first node of a first level of the system, defining a second fault model associated with a se... | 07/17/2007 |
| 7240261 | Scan chain diagnostics using logic paths A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to... | 07/03/2007 |
| 7234159 | Method and apparatus for controlling evaluation of protected intellectual property in hardware Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, systems, apparatus, met... | 06/19/2007 |
| 7216280 | Method of generating test patterns to efficiently screen inline resistance delay defects in complex ASICs A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STE) transition fault is detected, that specific fault is removed from a f... | 05/08/2007 |
| 7191374 | Method of and program product for performing gate-level diagnosis of failing vectors A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault ... | 03/13/2007 |
| 7184037 | Virtual environment navigation aid A virtual environment browser (64) holds a number of clip-in files (70, 72, 74) defining guide characters—locally generated visual aids to navigation that appear within a generated image of a virtual environment and follow a user's input (80) ... | 02/27/2007 |
| 7181585 | Defensive heap memory management A data structure, method and system are provided incorporating a general purpose memory allocator and defensive heap memory manager. This provides an ability to reliably detect various types of memory errors, dynamically enable or disable memory debugging, enhance s... | 02/20/2007 |
| 7171337 | Event-based automated diagnosis of known problems System events preceding occurrence of a problem are likely to be similar to events preceding occurrence of the same problem at other times or on other systems. Thus, the cause of a problem may be identified by comparing a trace of events preceding occurrence of the ... | 01/30/2007 |
| 7171587 | Automatic test system with easily modified software An automatic test system, such as might be used to test semiconductor devices as part of their manufacture. The test system uses instruments to generate and measure test signals. The automatic test system has a hardware and software architecture that allows instrume... | 01/30/2007 |
| 7162670 | IBIST interconnect and bridge fault detection scheme A method and mechanism for detecting interconnect and bridge defects. Contact points in a chip are assigned placement designation such that no two adjacent points have the same designation. A transmitter, receiver, and optional transmitter/receiver test are then run... | 01/09/2007 |
| 7158906 | Test method, test system, and program therefor In a test system, a test method, and a program for use in verifying states in a target, a predetermined state is previously defined as an intermediate state among states which can be taken by the target. On causing a transition to occur in the target from a previous... | 01/02/2007 |
| 7130923 | Method and apparatus for guessing correct URLs using tree matching The present invention assists a user in locating an intended address even where an address entered by the user is incorrect. In particular, in accordance with an embodiment of the present invention, an address structure entered by a user containing an existing domai... | 10/31/2006 |
| 7098878 | Semiconductor device and liquid crystal panel driver device A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which sig... | 08/29/2006 |
| 7072781 | Architecture for generating adaptive arbitrary waveforms A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG)... | 07/04/2006 |
| 7065690 | Fault detecting method and layout method for semiconductor integrated circuit The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on site... | 06/20/2006 |
| 7051924 | Value holding system, value holding method, value holding program, and transaction system A value holding system includes a receiving unit that receives an instruction to add or remove a value relating to a payment, a judging unit that judges whether the instruction is identical to a previously received instruction, and a rejecting unit that rejects the ... | 05/30/2006 |
| 7047469 | Method for automatically searching for and sorting failure signatures of wafers A method of searching for and sorting failure signatures of wafers is provided. First, a failure signature database is built up for recording a plurality of failure signature data, wherein each failure signature data includes a failure signature, a location field fo... | 05/16/2006 |
| 7036099 | Integrated circuit capable of locating failure process layers An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided ... | 04/25/2006 |
| 7017095 | Functional pattern logic diagnostic method A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is ac... | 03/21/2006 |
| 7007207 | Scheduling of transactions in system-level test program generation A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. ... | 02/28/2006 |
| 6973591 | On-chip emulator communication for debugging A debugging system comprising a host computer system and a target device, said target device having an embedded digital processor on an integrated circuit chip, an on-chip emulation device coupled to said digital processor, the on-chip emulation device being operabl... | 12/06/2005 |
| 6973592 | On-chip emulator communication An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said d... | 12/06/2005 |
| 6971054 | Method and system for determining repeatable yield detractors of integrated circuits An exemplary embodiment of the present invention is a method for testing an integrated circuit. The method includes generating a test pattern and generating a reference signature corresponding to the test pattern. An integrated circuit test is executed in response t... | 11/29/2005 |
| 6928581 | Innovative bypass circuit for circuit testing and modification An integrated circuit module is designed with bypass switches in critical places to route signals around specific circuit blocks, e.g. an automatic gain control (AGC) system and an anti-aliasing filter. If there had been significant problems with either block, it ca... | 08/09/2005 |
| 6925583 | Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data... | 08/02/2005 |
| 6920596 | Method and apparatus for determining fault sources for device failures A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate ... | 07/19/2005 |
