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| Number | Title | Issue Date |
| 5153886 | Visual display signal processing system and method A computer hardware-related device and method is used for regression testing techniques involving the testing of computer hardware and/or software application(s). Input data is received from a host, and is directed to software application(s) on a System U... | 10/06/1992 |
| 5103450 | Event qualified testing protocols for integrated circuits A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qual... | 04/07/1992 |
| 5090015 | Programmable array logic self-checking system A self checking electronically erasable programmable array logic (EEPAL) that comprises an input receiver, a programmable array, an error detection code storage array, an error detection circuitry, and error signalling circuitry is disclosed. The self che... | 02/18/1992 |
| 5084874 | Enhanced test circuit A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs ... | 01/28/1992 |
| 5081626 | System for detection and location of events A detector and locator system monitors sequential signals to detect and locate events. In a fault detector and locator embodiment, the system monitors the sequential states of multiples signals to detect a fault and to locate the source of a fault. A Hamm... | 01/14/1992 |
| 5051996 | Built-in-test by signature inspection (bitsi) A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If ... | 09/24/1991 |
| 5051997 | Semiconductor integrated circuit with self-test function Apparatus is disclosed for a self-test function internal to a semiconductor integrated circuit. The invention includes an internal random number generator for generating test data for use by a self-test program. As a result of the invention, external equi... | 09/24/1991 |
| 5047712 | Circuit for inverting the latter half of pattern output from device under test A circuit for inverting the latter half of an expected signal representative of an output expected for a device to be tested with regard to operation thereof by a tester comprises a first flip-flop having a D-input terminal supplied with an inverting sign... | 09/10/1991 |
| 5042034 | By-pass boundary scan design The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear fee... | 08/20/1991 |
| 5036479 | Modular automated avionics test system A modular automated test station permits a plurality of tests to be performed under program control on complex electronic assemblies such as avionics equipment and provides for calibration. Interactive prompts are displayed enabling test personnel with mi... | 07/30/1991 |
| 5034687 | Signature indicating circuit A circuit for testing signatures at a pin in a CMOS device where this device is operable when it is powered by a voltage within the predetermined range. During the test mode, a task voltage whose magnitude is below that of any voltage in the operating ran... | 07/23/1991 |
| 5006787 | Self-testing circuitry for VLSI units An application specific integrated circuit is provided on a chip where a combinatorial logic circuitry such as a RAM memory array, logic circuitry and control circuitry may be operated in the normal mode with the addition of a built-in, self-test feature ... | 04/09/1991 |
| 5001713 | Event qualified testing architecture for integrated circuits A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) i... | 03/19/1991 |
| 4993027 | Method and apparatus for determining microprocessor kernal faults Method and apparatus for testing the address/data paths between the ROM and CPU of a computer where the computer includes a first connector adapted to connect the ROM to the address/data paths so that data can be transferred between the CPU and the ROM vi... | 02/12/1991 |
| 4991175 | Signature analysis Digital signal processing apparatus which can be tested by signature analysis is arranged so that a predetermined number of its ROM locations have stored therein pre-selected values whereby the signature analysis is independent of the contents of the rema... | 02/05/1991 |
| 4982403 | Electrical circuit testing device and circuit comprising the said device A device for the testing of electrical circuits and a circuit comprising the said device are disclosed. The testing device is used to test electrical circuits by the generation of test vectors and the compression of the signal at the output of the device ... | 01/01/1991 |
| 4947106 | Programmatically generated in-circuit test of analog to digital converters A device and process for programmatically controlled in-circuit pin checks and gross functionality tests of analog to digital converters. The tests provide deterministic bit checks for higher order bits and non-deterministic bit checks of lower order bits... | 08/07/1990 |
| 4926425 | System for testing digital circuits Test node equipment is provided between successive component groups operating in cascade and each test node is connected to a data bus system through which test patterns can be provided by a test pattern generator and from which signals can be evaluated b... | 05/15/1990 |
| 4924469 | Semiconductor integrated circuit device In a system including LSIs, the signature register used for self-testing the LSI functions is assigned to one register accessible by a machine instruction. The signature is calculated in the self-test operation, and the calculation result is updated depen... | 05/08/1990 |
| 4918378 | Method and circuitry for enabling internal test operations in a VLSI chip A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunctio... | 04/17/1990 |
| 4910735 | Semiconductor integrated circuit with self-testing A semiconductor integrated circuit comprises a plurality of integrated circuit blocks constructed on a wafer. The integrated circuit blocks are electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a ... | 03/20/1990 |
| 4903266 | Memory self-test A system and method for on-chip self test of memory circuits is disclosed. Memory circuit testing is accomplished by using a random pattern generator based upon a primitive polynomial and including a linear feedback shift register having at least one stag... | 02/20/1990 |
| 4897842 | Integrated circuit signature analyzer for testing digital circuitry A system for testing digital circuitry includes a signature generator that is connected to a plurality of nodes in the circuit to be tested and that generates signature words unique to identical streams of binary data signals or clocking signals. A multip... | 01/30/1990 |
| 4887267 | Logic integrated circuit capable of simplifying a test A logic integrated circuit includes a FIFO type memory circuit provided for testing. A logic value at each test node is stored in the memory circuits during a write-in enable period set by a control signal from a flip-flop or an externally supplied contro... | 12/12/1989 |
| 4885712 | Method and apparatus for partial test-cause generation Disclosed is a test-cause generation method for implementing systematically the function test of logical devices. The method features the generation of partial test-causes for checking the functional relation at each state transition through the operation... | 12/05/1989 |
| 4873686 | Test assist circuit for a semiconductor device providing fault isolation In a test assist circuit for a semiconductor device, an address input selector (14a) is so switched that an external address signal is supplied to an address decoder (4) to address a memory circuit (3), while an input data selector (14b) is so switched th... | 10/10/1989 |
| 4872168 | Integrated circuit with memory self-test A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is w... | 10/03/1989 |
| 4864570 | Processing pulse control circuit for use in device performing signature analysis of digital circuits A processing pulse control circuit for use in treating indeterminate signature increments in an apparatus producing RPT signature analysis of digital circuits. A circuit to control clock pulses to processing devices is provided. The circuit includes a cou... | 09/05/1989 |
| 4847839 | Digital registers with serial accessed mode control bit A reconfigurable digital register that can be serially loaded has an additional bit associated with the register which holds information indicative of a mode of operation of the register. The mode control bit is located such that it can be serially loaded... | 07/11/1989 |
| 4835458 | Signature analysis technique for defect characterization of CMOS static RAM cell failures An error testing process for the testing of CMOS static RAM memories. Individual static RAM memory cells that have failed are isolated. A typical cell has six transistors, two access, two n-channel and two p-channel. The access transistors are allowed to ... | 05/30/1989 |
| 4817093 | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creat... | 03/28/1989 |
| 4802168 | Test signal generating circuit A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the ... | 01/31/1989 |
| 4801870 | Weighted random pattern testing apparatus and method A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals... | 01/31/1989 |
| 4791359 | Method of detecting possibly electrically-open connections between circuit nodes and pins connected to those nodes A method of detecting possibly electrically-open connections between circuit nodes and pins of components physically connected to the nodes. The pins include input pins and output pins, the input pins connected to corresponding input nodes and the output ... | 12/13/1988 |
| 4789821 | Test device for a combinatorial logic circuit and integrated circuit including such a device This device and method for testing a combinative logic circuit (4), includes on the one hand a circuit generating test sequences (30) for applying test logic signals to N inputs of the combinative logic circuit and, on the other hand, an output circuit (5... | 12/06/1988 |
| 4779273 | Apparatus for self-testing a digital logic circuit A method is disclosed that lends itself to efficient incorporation in digital logic networks to enable such networks to automatically test themselves in place. A register is incorporated in the network in such a manner that a data pattern loaded in the re... | 10/18/1988 |
| 4768196 | Programmable logic array Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaulated sequentially. A multiple input signature register which uses XQ +1 as ... | 08/30/1988 |
| 4763066 | Automatic test equipment for integrated circuits The apparatus (10) includes a semiconductor tester (12) which in operation produces an analog signature signal relative to a circuit node of an electronic circuit, such as a pin connection of an integrated circuit. The analog signature signal is the resul... | 08/09/1988 |
| 4763288 | System for simulating electronic digital circuits A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a vide... | 08/09/1988 |
| 4761607 | Apparatus and method for inspecting semiconductor devices A semiconductor device inspecting apparatus includes a signal input for an LSI device, a comparator used to compare an LSI device output with an expected value, an X-Y stage for moving the LSI device in an X direction or a Y direction, a probe for non-con... | 08/02/1988 |
