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| Number | Title | Issue Date |
| 4754215 | Self-diagnosable integrated circuit device capable of testing sequential circuit elements In a self-diagnosable integrated circuit device comprising sequential circuit elements in an internal logic circuit, a first test pattern signal is successively produced in a test mode from a test pattern generating circuit and stored into the sequential ... | 06/28/1988 |
| 4745355 | Weighted random pattern testing apparatus and method A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals... | 05/17/1988 |
| 4724380 | Integrated circuit having a built-in self test design An integrated circuit having a built-in self test design, the integrated circuit including a combinatorial logic circuit, a first register coupled to an output of the combinatorial logic circuit and a feedback path via which output signals from the first ... | 02/09/1988 |
| 4718065 | In-line scan control apparatus for data processor testing Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data p... | 01/05/1988 |
| 4715035 | Method for the simulation of an error in a logic circuit and a circuit arrangement for implementation of the method A method for the simulation of an error in a logic circuit which comprises a bus optionally connectible to different logic levels, utilizes the assistance of input bit patterns from which output bit patterns are derived via a simulation model containing t... | 12/22/1987 |
| 4701916 | Digital integrated circuit with multi-mode register A digital integrated circuit comprises a number of registers each of which comprises several data bits and at least one control bit cell. In a normal operation state, all the registers act as parallel input/output registers. In a SHIFT state, the data bit... | 10/20/1987 |
| 4688222 | Built-in parallel testing circuit for use in a processor The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the for... | 08/18/1987 |
| 4641306 | Circuit arrangement for testing a digital circuit Circuit arrangement for dynamic real time testing of a synchronous digital circuit having a clock pulse input, a stimulus input and a circuit node at which a digital test signal is produced after a time delay of ͌ seconds relative to the time of receipt ... | 02/03/1987 |
| 4641254 | Test set for a navigational satellite receiver A test set including a digital card tester section and a satellite simula section is used to detect the reduced capabilities of an associated navigational satellite receiver and to isolate malfunctions therein. The digital card tester section is configur... | 02/03/1987 |
| 4635261 | On chip test system for configurable gate arrays An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plural... | 01/06/1987 |
| 4622652 | Signal identification A device and process for identifying signals in microprocessors-based circuits includes a probe, a display a target interface and a control system based on a similar microprocessor. Sets of signal patterns are impressed on lines in the target system. The ... | 11/11/1986 |
| 4608691 | Signature analyzer card A signature analyzer card 102 having sixteen cycle redundancy circuits 106 embodied within a cycle redundancy check generator 104 for serially receiving two thousand and forty-eight binary words 54 from a logic circuit card 22 under test when the cycle re... | 08/26/1986 |
| 4601033 | Circuit testing apparatus employing signature analysis Apparatus is disclosed for testing an electrical circuit by means of signature analysis. Responses to a sequence of test patterns from the circuit under test are supplied to a linear feedback signature register (LFSR) which produces a signature signal at ... | 07/15/1986 |
| 4601034 | Method and apparatus for testing very large scale integrated memory circuits Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at leas... | 07/15/1986 |
| 4598401 | Circuit testing apparatus employing signature analysis Apparatus is disclosed for testing an electrical circuit by means of signature analysis. Responses to a sequence of test patterns from the circuit under test are supplied to a linear feedback signature register (LFSR) which produces a signature signal at ... | 07/01/1986 |
| 4597080 | Architecture and method for testing VLSI processors A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation o... | 06/24/1986 |
| 4594711 | Universal testing circuit and method A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for a... | 06/10/1986 |
| 4580274 | Transceiver test device A device for testing the digital waveforms in a special purpose multi-channel transceiver system designed to operate in a tactical environment. As selected waveforms are presented to the test device, they are randomized over a fixed time period creating a... | 04/01/1986 |
| 4551838 | Self-testing digital circuits In order to test a digital circuit, such as a digital logic circuit (e.g., 100), for faults, during the first three cycles of a test operation of many cycles in duration, a predetermined input word is delivered to the input terminals of the logic circuit.... | 11/05/1985 |
| 4551837 | High speed operational recurring signature evaluator for digital equipment tester The high speed operational recurring signature evaluation provides digital sub-systems including a data compressor and a controller. These subsystems are employed with a portable service processor (PSP) which is a standard piece of test equipment in this ... | 11/05/1985 |
| 4539517 | Method for testing an integrated circuit chip without concern as to which of the chip's terminals are inputs or outputs Methods are disclosed which provide for testing a wide variety of different types of electrical circuit devices, such as PROM integrated circuit chips, with very little if any programming being required, and without concern as to which of the terminals of... | 09/03/1985 |
| 4534030 | Self-clocked signature analyzer A method and circuit for using signature analysis testing techniques without deriving start/stop and clock signals from the device under test. In this invention, a start signal is derived from the output data stream by configuring that data stream to indi... | 08/06/1985 |
| 4527272 | Signature analysis using random probing and signature memory A circuit test system using signature analysis allows random probing to detect faults in an assembly under test. Test points on a properly working assembly are probed at random and the signatures obtained are listed in a memory or storage media. Thereafte... | 07/02/1985 |
| 4519078 | LSI self-test method A method of self-testing LSI circuits and/or systems in which LSI and discrete logic circuits are used that incorporates internally generated pseudorandom sequences as test vectors to stimulate the logic circuits under test. Responses to the test vectors ... | 05/21/1985 |
| 4513418 | Simultaneous self-testing system The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.... | 04/23/1985 |
| 4510572 | Signature analysis system for testing digital circuits A signature analyzer for testing digital circuits. The analyzer includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then... | 04/09/1985 |
| 4503536 | Digital circuit unit testing system utilizing signature analysis A system for testing digital circuit units at the design speed of the circuit. A first memory stores a minimized set of optimum generated predetermined test patterns for application to a unit under test. A second memory stores expected signature patterns ... | 03/05/1985 |
| 4503537 | Parallel path self-testing system The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generat... | 03/05/1985 |
| 4498172 | System for polynomial division self-testing of digital networks A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system ... | 02/05/1985 |
| 4493078 | Method and apparatus for testing a digital computer A system for on-line, concurrent self-testing of a computer is disclosed which is capable of checking the "test kernel" of the computer; that is, the portion of the computer that must be fault-free in order for the computer to test itself with a self-test... | 01/08/1985 |
| 4441183 | Apparatus for testing digital and analog circuits A high-speed, high-resolution testing circuit for both analog and digital circuit packs is described. The testing circuit, which employs data compression techniques, comprises a shift register (22) having an overall length selectively variable under progr... | 04/03/1984 |
| 4441074 | Apparatus for signature and/or direct analysis of digital signals used in testing digital electronic circuits A digital circuit tester for performing signature analysis is provided with a memory (32) for storing successive samples at 256-bit intervals of the progressively evolving CRC signature of a signal in the circuit under test. Comparison with the same seque... | 04/03/1984 |
| 4433413 | Built-in apparatus and method for testing a microprocessor system Built-in test apparatus is provided for testing the overall functional operation of a microprocessor system which has microprocessor, RAM, PROM, address latch, I/O, timer, multiple bus arbitration and other circuits in it. To the microprocessor system are... | 02/21/1984 |
| 4410991 | Supervisory control apparatus Apparatus for monitoring and controlling the operation of a program-controlled computer. The program causes the computer to produce a signature waveform characteristic of proper computer operation at a dedicated output. The presence or absence of this wav... | 10/18/1983 |
| 4320509 | LSI Circuit logic structure including data compression circuitry A logic structure for an LSI digital circuit includes data compression circuitry for deriving a signature word from the data on a multiplicity of internal nodes which are not directly accessible from the terminals of the circuit. The signature word provid... | 03/16/1982 |
| 4216539 | In-circuit digital tester An apparatus for the automatic, in-circuit testing of the electrical properties of complex digital integrated circuit assemblies is disclosed. A programmed processor is provided to control a set of selectable switches, which connect selected nodes of a ci... | 08/05/1980 |
| 4194113 | Method and apparatus for isolating faults in a logic circuit A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature... | 03/18/1980 |
| 4192451 | Digital diagnostic system employing signature analysis A digital diagnostic system employs signature analysis for locating faults at the system, module, or circuit component level in electronic equipment. Predetermined correct signatures and diagnostic decision tree information for a particular device under t... | 03/11/1980 |
| 4183460 | In-situ test and diagnostic circuitry and method for CML chips An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three par... | 01/15/1980 |
| 4108359 | Apparatus for verifying the execution of a sequence of coded instructions Apparatus for detecting errors in the execution of a sequence of coded inuctions. The apparatus includes a feed-back shift register to generate a digital sequence which is combined with the sequence of instructions to be verified to compute a unique sequ... | 08/22/1978 |
