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| Number | Title | Issue Date |
| 7222276 | Scan test circuit including a control test mode A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (... | 05/22/2007 |
| 7219281 | Boundary scan of integrated circuits An improved 2-bit boundary scan test circuit capable of applying boundary scan test vectors to the input of the core logic of a circuit, using a multiplexer for selectively coupling the output of a boundary scan register to the input of a boundary scan register or t... | 05/15/2007 |
| 7219282 | Boundary scan with strobed pad driver enable A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to t... | 05/15/2007 |
| 7219283 | IC with TAP, STP and lock out controlled output buffer Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an ou... | 05/15/2007 |
| 7219269 | Self-calibrating strobe signal generator A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator ... | 05/15/2007 |
| 7219258 | Method, system, and product for utilizing a power subsystem to diagnose and recover from errors A method, system, and computer program product are disclosed for diagnosing and recovering from I/O subsystem errors. A data processing system includes a computer which includes a power subsystem and at least one I/O subsystem. A determination is made that an error ... | 05/15/2007 |
| 7219278 | Configurator arrangement and approach therefor A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths. According to an example embodiment of the present invention, a configurator arrangement (100) is prog... | 05/15/2007 |
| 7219280 | Integrated circuit with test signal routing module Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a routing module. The routing module is configured to receive test input vectors, select at least one logic block, select a routi... | 05/15/2007 |
| 7216275 | Method and apparatus for accessing hidden data in a boundary scan test interface An apparatus and method for accessing hidden data in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test i... | 05/08/2007 |
| 7213183 | Integrated circuit The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register ... | 05/01/2007 |
| 7210079 | Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and de... | 04/24/2007 |
| 7206983 | Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments... | 04/17/2007 |
| 7203880 | Generating an abbreviated netlist including pseudopin inputs and output nodes A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonpr... | 04/10/2007 |
| 7203913 | Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-f... | 04/10/2007 |
| 7202688 | Output buffer circuit having signal path used for testing and integrated circuit and test method including the same An output buffer circuit includes a signal path used for testing and designed for outputting output signals at predetermined logic levels in response to internal output signals from an internal logic circuit. The output buffer circuit and includes a first control in... | 04/10/2007 |
| 7200235 | Error-checking and correcting decryption-key memory for programmable logic devices Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. Th... | 04/03/2007 |
| 7197674 | Method and apparatus for conditioning of a digital pulse An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode sig... | 03/27/2007 |
| 7197684 | Single-ended transmission for direct access test mode within a differential input and output circuit An integrated circuit, among other embodiments, includes an output circuit to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact du... | 03/27/2007 |
| 7191372 | Integrated data download A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Suc... | 03/13/2007 |
| 7191373 | Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises u... | 03/13/2007 |
| 7191371 | System and method for sequential testing of high speed serial link core A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter... | 03/13/2007 |
| 7191268 | Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host... | 03/13/2007 |
| 7190583 | Self contained, liquid to air cooled, memory test engineering workstation Although various embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments discl... | 03/13/2007 |
| 7191265 | JTAG and boundary scan automatic chain selection A printed circuit board (PCB) may be used in a first mode where boundary scan techniques are used to externally program and/or test devices on the PCB, or a second mode where an internal source programs devices using boundary scan techniques. In one implementation, ... | 03/13/2007 |
| 7188286 | Accelerated scan circuitry and method for reducing scan test data volume and execution time An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired C... | 03/06/2007 |
| 7188277 | Integrated circuit An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the de... | 03/06/2007 |
| 7188285 | Scan test circuit with reset control circuit A scan test circuit includes a scan flip-flop that receives a reset signal, a data signal, a scan data signal, and a scan shift enable signal selecting either the data signal or the scan data signal. A reset control circuit controls the reset signal according to the... | 03/06/2007 |
| 7187193 | MCU test device for multiple integrated circuit chips A testing device for testing integrated circuits is disclosed including a first board configured to connect to a specific integrated circuit being tested. A second board is removably connected to the first board and is configurable to test a variety of integrated ci... | 03/06/2007 |
| 7188043 | Boundary scan analysis A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors ... | 03/06/2007 |
| 7183792 | Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mod... | 02/27/2007 |
| 7185243 | Testing implementation suitable for built-in self-repair (BISR) memories A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially outpu... | 02/27/2007 |
| 7185249 | Method and apparatus for secure scan testing A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from ... | 02/27/2007 |
| 7185253 | Compacting circuit responses Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrat... | 02/27/2007 |
| 7185251 | Method and apparatus for affecting a portion of an integrated circuit In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting... | 02/27/2007 |
| 7185250 | Tap with separate scan cell in series with instruction register An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hie... | 02/27/2007 |
| 7181664 | Method on scan chain reordering for lowering VLSI power consumption A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method include... | 02/20/2007 |
| 7181661 | Method and system for broadcasting data to multiple tap controllers A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the pl... | 02/20/2007 |
| 7178075 | High-speed level sensitive scan design test scheme with pipelined test clocks This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipel... | 02/13/2007 |
| 7177965 | Linking addressable shadow port and protocol for serial bus networks Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection... | 02/13/2007 |
| 7174492 | AC coupled line testing using boundary scan test methodology Testing AC coupled interconnects using boundary scan test methodology. Specially designed AC boundary scan cells and boundary scan logic are used. These are compatible with IEEE Standard 1149.1 testing. An AC_EXTEST method is used to determine the reliability of the... | 02/06/2007 |
