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| Number | Title | Issue Date |
| 5270642 | Partitioned boundary-scan testing for the reduction of testing-induced damage A partitioned boundary-scan interconnect test method for loaded printed wiring boards (PWB's) is disclosed which reduces testing-induced damage to electronic components. The method is adapted to expeditiously identify all short-circuits on a PWB. The part... | 12/14/1993 |
| 5260948 | Bidirectional boundary-scan circuit A boundary-scan circuit for a bidirectional pin of an integrated circuit which uses fewer standard cells if a cell design is considered, or fewer devices if non-standard cell integrated circuits are considered. In either case, the present invention provid... | 11/09/1993 |
| 5260950 | Boundary-scan input circuit for a reset pin A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even ... | 11/09/1993 |
| 5260947 | Boundary-scan test method and apparatus for diagnosing faults in a device under test An apparatus for diagnosing faults in a device equipped with boundary-scan test capability stores serial test data upon detection of a fault in a device under test (DUT). Test data corresponding to a frame vector associated with the fault is formatted so ... | 11/09/1993 |
| 5260649 | Powered testing of mixed conventional/boundary-scan logic The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being ... | 11/09/1993 |
| 5254942 | Single chip IC tester architecture An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect re... | 10/19/1993 |
| 5222068 | Processor circuit A processor circuit includes multiplexers, demultiplexers, boundary-scan registers, register cells as well as corresponding control logic and a processor core. This permits a self-test of the componentry to which it belongs and a production test of the co... | 06/22/1993 |
| 5220281 | Boundary scan cell for bi-directional input/output terminals A boundary scan cell is disclosed. Bi-directional input/output terminals are connected to bi-directional input/output terminals of a logic circuit subject to test in order to store test data or a test result in a first latch circuit, the output impedance ... | 06/15/1993 |
| 5202625 | Method of testing interconnections in digital systems by the use of bidirectional drivers A bidirectional boundary scan circuit cell for use in boundary scan testing of device interconnections including a scan flip-flop, a first multiplexer responsive to the scan flip-flop and to a device output if the associated pin is for an output function ... | 04/13/1993 |
| 5198759 | Test apparatus and method for testing digital system A testing apparatus and method for testing of assemblies (BG1, BG2 . . . , BGn) in digital electronic systems, which permits a test on a system level without a fixed pre-setting of the number and position of the assemblies to be tested. On each assembly, ... | 03/30/1993 |
| 5172377 | Method for testing mixed scan and non-scan circuitry A method of performing in-circuit testing of interior points of circuit boards containing both boundary-scan and non-scan components that utilizes the boundary-scan facility. The testing procedure involves isolation of the non-scan components and either d... | 12/15/1992 |
| 5132635 | Serial testing of removable circuit boards on a backplane bus A system for controlling daisy-chain testing of removable printed circuit boards installed along a backplane bus facilitates the use of serial testing methods for circuit boards which are designed according to boundary-scan testing standards. The system a... | 07/21/1992 |
| 5130988 | Software verification by fault insertion An integrated circuit having boundary-scan facilities in accordance with IEEE Standard 1149.1, has its boundary scan chain configured to permit fault insertion testing of diagnostic and maintenance software. Each Scan cell includes storage devices for sto... | 07/14/1992 |
| 5115191 | Testing integrated circuit capable of easily performing parametric test on high pin count semiconductor device A boundary-scan-testing integrated circuit adapted to both a functional test of an entire IC chip and a parametric test for input and output buffers, connected to pads of the IC chip, in a periphery cell area of the IC chip. First memory circuits are resp... | 05/19/1992 |
| 5115435 | Method and apparatus for bus executed boundary scanning A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transf... | 05/19/1992 |
| 5109190 | Semiconductor apparatus including semiconductor integrated circuit and operating method thereof A semiconductor apparatus including a semiconductor integrated circuit is disclosed. The semiconductor integrated circuit includes a circuit block, a plurality of boundary scan registers, a system data terminal, a test signal terminal and a control circui... | 04/28/1992 |
| 5103450 | Event qualified testing protocols for integrated circuits A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qual... | 04/07/1992 |
| 5084874 | Enhanced test circuit A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs ... | 01/28/1992 |
| 5048021 | Method and apparatus for generating control signals A method is disclosed for generating a control signal (TMS) which may be used to control the test activity of boundary scan system (10). The method is initiated by loading a multi-bit control macro (STI, DTI or DSTI) into a register (38) whose output is c... | 09/10/1991 |
| 5042034 | By-pass boundary scan design The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear fee... | 08/20/1991 |
| 5001713 | Event qualified testing architecture for integrated circuits A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) i... | 03/19/1991 |
| 4945536 | Method and apparatus for testing digital systems In methods and apparatus for testing a digital system, system terminals used for coupling input signals into the system and output signals out of the system during normal operation of the system are connected in parallel to a single boundary register. The... | 07/31/1990 |
| 4879717 | Testable carriers for integrated circuits A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected t... | 11/07/1989 |
| 4872169 | Hierarchical scan selection A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the desig... | 10/03/1989 |
| 4701921 | Modularized scan path for serially tested logic circuit A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) pro... | 10/20/1987 |
