Class 714/727 - Boundary scan

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter where selected components in a circuit are
No. of patents: 905
Last issue date: 05/08/2012

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Number	Title	Issue Date
7958419	Entering a shift-DR state in one of star connected components A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura...	06/07/2011
7958420	Clock delay circuits and multiplexer connected to boundary scan circuitry A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producin...	06/07/2011
7949919	Microelectronic device and pin arrangement method thereof The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test s...	05/24/2011
7949918	Asynchronous communication using standard boundary architecture cells An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core pr...	05/24/2011
7949917	Maintaining data coherency in multi-clock systems A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock ...	05/24/2011
7945831	Gating TDO from plural JTAG circuits Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary sca...	05/17/2011
7945832	Interface to full and reduced pin JTAG devices The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The acce...	05/17/2011
7941717	IC testing methods and apparatus A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is ...	05/10/2011
7937635	Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ...	05/03/2011
7930606	Selectively debugging processor cores through instruction codes A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m≧2) and less than the total number of m bits a...	04/19/2011
7925942	Augmentation instruction shift register with serial and two parallel inputs An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested...	04/12/2011
7925943	Multiplexer connecting TDI or AX1/TDI to data and instruction registers The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary...	04/12/2011
7917819	JTAG test architecture for multi-chip pack A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be...	03/29/2011
7917820	Testing an embedded core A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. Th...	03/29/2011
7913135	Interconnections for plural and hierarchical P1500 test wrappers A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bo...	03/22/2011
7913134	Test circuit capable of sequentially performing boundary scan test and test method thereof A boundary scan test circuit is capable of sequentially performing a boundary scan test with respect to semiconductor integrated circuits bonded to both surfaces of a memory board. In order to reduce a boundary scan test time, the boundary scan test circuit includes...	03/22/2011
7908533	Processor to JTAG test access port interface Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is c...	03/15/2011
7900106	Accessing sequential data in a microcontroller System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies a...	03/01/2011
7890825	Data summing boundary cell Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit	02/15/2011
7890824	Asynchronous communication apparatus using JTAG test data registers An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provid...	02/15/2011
7877652	Detection circuit and method for AC coupled circuitry Standardized scan cell logic is enabled to test board-level and circuit-level AC interfaces built into integrated CMOS circuits by verification of high-speed AC coupled non-CMOS logic level signals driven onto non-CMOS logic level AC coupled interconnects in those c...	01/25/2011
7877653	Address and TMS gating circuitry for TAP control circuit The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands fo...	01/25/2011
7877654	Selectable JTAG or trace access with data store and output An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning ci...	01/25/2011
7873889	JTAG bus communication method and apparatus The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an ...	01/18/2011
7870450	High speed double data rate JTAG interface A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from th...	01/11/2011
7870448	In system diagnostics through scan matrix A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in ...	01/11/2011
7870449	IC testing methods and apparatus A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received...	01/11/2011
7865791	Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be...	01/04/2011
7856581	Methods and apparatuses for external test methodology and initialization of input-output circuits Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on th...	12/21/2010
7853847	Methods and apparatuses for external voltage test of input-output circuits Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on th...	12/14/2010
7836369	Device and method for configuring input/output pads A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information...	11/16/2010
7831875	Interconnections for plural and hierarchical P1500 test wrappers A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bo...	11/09/2010
7827453	Core test circuits controlling boundary and general external scan circuits An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP le...	11/02/2010
7818641	Interface to full and reduce pin JTAG devices The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The acce...	10/19/2010
7797602	Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG...	09/14/2010
7788559	Test access mechanisms, associated controllers and a selector A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. T...	08/31/2010
7783947	Controller applying stimulus data while continuously receiving serial stimulus data An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the...	08/24/2010
7783948	Removeable and replaceable tap domain selection circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap ...	08/24/2010
7779321	Entering command based on number of states in advanced mode A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further comprises an interface adapter counting a number of inert scans in the command window, and the number of in...	08/17/2010
7774664	Separate scan cell in series with TAP instruction register An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hie...	08/10/2010

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Class 714/727 - Boundary scan