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| Number | Title | Issue Date |
| 7129746 | System-on-a-chip integrated circuit including dual-function analog and digital inputs An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconne... | 10/31/2006 |
| 7126856 | Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array A field-programmable gate array (FPGA) having an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of the row driver... | 10/24/2006 |
| 7124340 | Low pin count, high-speed boundary scan testing In a method for testing a testable electronic device having a first and a second plurality of test a arrangements a first shift register (110) is used in parallel with a second shift register (130) to time-multiplex a first test vector (102) and... | 10/17/2006 |
| 7124339 | Scan path circuit and semiconductor integrated circuit comprising the scan path circuit Each of D flip-flops (FFs) 13a to 13f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal h... | 10/17/2006 |
| 7123055 | Impedance-matched output driver circuits having coarse and fine tuning control Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein responsive to a ... | 10/17/2006 |
| 7120844 | System and method for performing scan test with single scan clock A logic system for performing scan test with single scan clock and related method. The logic system includes a first clock domain, which performs logic operations and scan tests with a first clock signal, and a second clock domain, which performs logic operations wi... | 10/10/2006 |
| 7120829 | Failure propagation path estimate system The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realiz... | 10/10/2006 |
| 7120557 | Systems and methods for analyzing data of a SAS/SATA device Systems and methods for analyzing data passing between an SAS/SATA device and a plurality of other devices are presented. A system includes a plurality of physical interfaces configured for passing data between the SAS/SATA device and the other devices. The system a... | 10/10/2006 |
| 7119398 | Power-up and power-down circuit for system-on-a-chip integrated circuit A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to t... | 10/10/2006 |
| 7120843 | IC with scan distributor and scan collector circuitry Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan... | 10/10/2006 |
| 7117413 | Wrapped core linking module for accessing system on chip test A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control reg... | 10/03/2006 |
| 7117274 | Graphical user interface and approach therefor A circuit testing and control approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths. According to an example embodiment of the present invention, graphical user interface (GUI) (... | 10/03/2006 |
| 7116181 | Voltage- and temperature-compensated RC oscillator circuit An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a... | 10/03/2006 |
| 7117412 | Flip-flop circuit for capturing input signals in priority order A flip-flop circuit includes first and second logic gates, a first selection circuit and a latch circuit. The first logic gate executes a logic operation on a first data signal and a first control signal. The second logic gate executes a logic operation on a second ... | 10/03/2006 |
| 7114109 | Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149.1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected ... | 09/26/2006 |
| 7111217 | Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selec... | 09/19/2006 |
| 7109771 | Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a... | 09/19/2006 |
| 7109754 | Synchronization of programmable multiplexers and demultiplexers Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output ... | 09/19/2006 |
| 7111216 | Scan controller and integrated circuit including such a controller An integrated circuit is provided in which a scan controller for controlling a scan test is integrated within the integrated circuit and shares the same input pins as a serial programmable interface of the integrated circuit. ... | 09/19/2006 |
| 7107503 | Boundary scan with ground bounce recovery A system for recovering from ground bounce during a boundary scan test is disclosed that includes operationally transitioning a Test Access Port controller from any of at least three undetermined controller states induced by the ground bounce to a determined control... | 09/12/2006 |
| 7107166 | Device for testing LSI to be measured, jitter analyzer, and phase difference detector LSI test equipment can acquire output data of an LSI as a device under test by a clock signal output from the LSI to be measured and acquire measurement data synchronously with the output data having jitter. The LSI test equipment includes a clock side time interpol... | 09/12/2006 |
| 7106108 | Semiconductor integrated circuit and evaluation method of wiring in the same An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second ... | 09/12/2006 |
| 7103864 | Semiconductor device, and design method, inspection method, and design program therefor A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circu... | 09/05/2006 |
| 7103814 | Testing logic and embedded memory in parallel Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between lo... | 09/05/2006 |
| 7102391 | Clock-generator architecture for a programmable-logic-based system on a chip A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic bloc... | 09/05/2006 |
| 7102384 | Non-volatile memory architecture for programmable-logic-based system on a chip A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory ... | 09/05/2006 |
| 7102555 | Boundary-scan circuit used for analog and digital testing of an integrated circuit Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is... | 09/05/2006 |
| 7100027 | System and method for reproducing system executions using a replay handler Methods and systems for replaying arbitrary system executions are disclosed. A system includes a storage element, a memory hierarchy and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The proces... | 08/29/2006 |
| 7099801 | Medical testing internet server system and method Server apparatus coupled to the Internet is operated to provide medical testing. Medical test measurement data is uploaded to the central server from remote locations via patient Internet apparatus via the Internet. The server selects a computer program algorithm to... | 08/29/2006 |
| 7099189 | SRAM cell controlled by non-volatile memory cell First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupl... | 08/29/2006 |
| 7096139 | Testing apparatus A testing apparatus having testing module slots onto which different types of testing modules are selectively mounted includes controlling modules for supplying control signals to the testing modules mounted on the testing module slots. The control signals are used ... | 08/22/2006 |
| 7095718 | Client/server scan software architecture The inventive interface connects a client system with the server computer. The server computer includes the JTAG scan program, and can issue scan tests to the desired device under test. Thus, the user can remotely operate the JTAG tool, and can use the unix shell or... | 08/22/2006 |
| 7093084 | Memory implementations of shift registers A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the re... | 08/15/2006 |
| 7089473 | Method and apparatus for testing a circuit using a die frame logic analyzer A die frame logic analyzer unit. For one aspect, a programmable logic analyzer unit is provided, wherein at least a first portion of the programmable logic analyzer unit is provided in a die frame. The programmable logic analyzer unit is to test a function of an int... | 08/08/2006 |
| 7089472 | Method and circuit for testing a chip A circuit for testing a chip. The chip has an intellectual product circuit module, and the circuit has a multiplexer controller, several registers and a MUX finite state machine controller to configure these registers in different states according to the test patter... | 08/08/2006 |
| 7089470 | Programmable test pattern and capture mechanism for boundary scan Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC b... | 08/08/2006 |
| 7089463 | Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnecti... | 08/08/2006 |
| 7088091 | Testing a multi-channel device In one embodiment, a method includes routing first test data from a first channel of a device to a second channel of the device, and outputting the first test data from the second channel. The device, in one embodiment, may be a mixed signal device and the test data... | 08/08/2006 |
| 7085980 | Method and apparatus for determining the failing operation of a device-under-test The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment execu... | 08/01/2006 |
| 7085976 | Method and apparatus for hardware co-simulation clocking Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardwa... | 08/01/2006 |
