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| Number | Title | Issue Date |
| 7095718 | Client/server scan software architecture The inventive interface connects a client system with the server computer. The server computer includes the JTAG scan program, and can issue scan tests to the desired device under test. Thus, the user can remotely operate the JTAG tool, and can use the unix shell or... | 08/22/2006 |
| 7093156 | Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that ... | 08/15/2006 |
| 7093176 | Programmable test for memories A programmable built in self test, BIST, system for testing a memory, comprises an instruction register formed in the same chip as the memory; a circuit for loading the register by successive instructions, each instruction comprising at least one address control fie... | 08/15/2006 |
| 7091745 | Indicating completion of configuration for programmable devices Various approaches for indicating completion of configuration of programmable logic devices are disclosed. In one embodiment, a plurality of configuration memory cells are arranged for storage of a configuration bitstream for implementing a circuit design on the pro... | 08/15/2006 |
| 7089140 | Programmable logic device and method of testing a programmable logic device A programmable logic device includes a functional block, which does not form part of an embedded processor, which can perform a testing function on other functional blocks of the programmable logic device. Thus, the test block can read stored data values from regist... | 08/08/2006 |
| 7089474 | Method and system for providing interactive testing of integrated circuits A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorith... | 08/08/2006 |
| 7087954 | In service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu... | 08/08/2006 |
| 7085976 | Method and apparatus for hardware co-simulation clocking Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardwa... | 08/01/2006 |
| 7081771 | Upgradeable and reconfigurable programmable logic device Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and i... | 07/25/2006 |
| 7082556 | System and method of detecting a bit processing error The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiv... | 07/25/2006 |
| 7078929 | Interface controller using JTAG scan chain In a programmable logic device system, including a programmable logic device, a configuration memory device, for storing configuration information, and a host computer system, for generating updated configuration information, the programmable logic device has a JTAG... | 07/18/2006 |
| 7074673 | Service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu... | 07/11/2006 |
| 7076751 | Chip debugging using incremental recompilation While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The ... | 07/11/2006 |
| 7076710 | Non-binary address generation for ABIST Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an add... | 07/11/2006 |
| 7075829 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 07/11/2006 |
| 7068544 | Flash memory with low tunnel barrier interpoly insulators Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing th... | 06/27/2006 |
| 7065687 | Method for replacing defective memory cells in data processing apparatus A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memo... | 06/20/2006 |
| 7061815 | Semiconductor memory device providing redundancy An improved semiconductor memory device providing row/column redundancy. The device includes a plurality of data latches arranged in a row-column matrix connected to a set of bitlines/global bitlines interfacing to read/write circuitry, at least two redundant row/co... | 06/13/2006 |
| 7062719 | Graphically defining a route through one or more switch devices One embodiment of the present invention comprises a system and method for graphically defining a route through one or more switch devices. the user may interact at a high level with a graphical user interface of a visual route editor to graphically create the route.... | 06/13/2006 |
| 7062692 | Duty cycle characterization and adjustment Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be pr... | 06/13/2006 |
| 7058856 | Semiconductor circuit with flash ROM and improved security for the contents thereof This invention provides a micro controller in which a JTAG (Joint Test Action Group) port becomes available through a specific operation even after a security bit is set. More specifically, an embodiment of this invention provides a micro controller wherein: when an... | 06/06/2006 |
| 7051153 | Memory array operating as a shift register A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected betw... | 05/23/2006 |
| 7049543 | Method of defining features on materials with a femtosecond laser The invention relates to a pulsed laser ablation method of metals and/or dielectric films from the surface of a wafer, printed circuit board or a hybrid substrate. By utilizing a high-energy ultra-short pulses of laser light, such a method can be used to manufacture... | 05/23/2006 |
| 7047464 | Method and system for use of a field programmable function within an application specific integrated circuit (ASIC) to access internal signals for external observation and control An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality... | 05/16/2006 |
| 7047465 | Methods for using defective programmable logic devices by customizing designs based on recorded defects Methods for utilizing PLDs with localized defects. Each PLD has a unique identifier. In one embodiment, a PLD provider tests a series of PLDs, selecting those having localized defects and recording the location of each detected defect for each defective PLD in a def... | 05/16/2006 |
| 7042043 | Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ... | 05/09/2006 |
| 7039842 | Measuring propagation delays of programmable logic devices Methods are described herein, for improving the accuracy of propagation delay measurements of programmable electronic devices in a production environment. In one method, a built-in self-test is implemented by configuring an oscillator and a counter connected to each... | 05/02/2006 |
| 7039841 | Tester system having multiple instruction memories An apparatus for testing an integrated circuit includes a sequence control logic unit having an output channel connectable to an input pin of a device under test, a first memory to store a first instruction set comprising instructions executable by the sequence cont... | 05/02/2006 |
| 7036046 | PLD debugging hub User logic within a PLD is debugged by way of the hub. The PLD includes a serial interface (such as a JTAG port) that communicates with a host computer. Any number of client modules are within the PLD and provide instrumentation for the PLD. A module is a logic anal... | 04/25/2006 |
| 7036062 | Single board DFT integrated circuit tester A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal... | 04/25/2006 |
| 7036059 | Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays SEU mitigation, detection, and correction techniques are disclosed. The mitigation techniques include: triple redundancy of a logic path is extended the length of the FPGA to avoid weak points susceptible to SEU effects; triple logic module and feedback redundancy p... | 04/25/2006 |
| 7035787 | Emulation components and system including distributed routing and configuration of emulation resources Data processing resources are distributively provided to an emulation system to locally and correspondingly generate configuration signals to configure selected ones of reconfigurable logic and interconnect resources of corresponding collections of reconfigurable lo... | 04/25/2006 |
| 7027328 | Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch... | 04/11/2006 |
| 7027947 | Integrated circuit testing method, program, storing medium, and apparatus An ATPG unit permits allocation of a don't care X as a state for activating a propagating path of a failure and, after a change in network, transfers the state from the don't care X to an uncontrol value, thereby activating the propagating path of the failure. Furth... | 04/11/2006 |
| 7024330 | Method and apparatus for decreasing automatic test equipment setup time In automatic test equipment (ATE), the current state of all configurable hardware components is maintained in one or more status registers. A configuration interface operates between the ATE test program and the hardware components. The test program issues instructi... | 04/04/2006 |
| 7020818 | Method and apparatus for PVT controller for programmable on die termination Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die t... | 03/28/2006 |
| 7015719 | Tileable field-programmable gate array architecture An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and... | 03/21/2006 |
| 7017138 | Dynamically determining a route through one or more switch devices at program execution time A system and method for dynamically determining a route through one or more switch devices at program execution time. A program operable to perform a programmatic request to dynamically determine a route may be created. For example, the request may specify a first e... | 03/21/2006 |
| 7010732 | Built-in test support for an integrated circuit Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to th... | 03/07/2006 |
| 7007203 | Error checking in a reconfigurable logic signal processor (RLSP) A reconfigurable logic signal processor system (RLSP) (100) and method of error checking same in accordance with certain embodiments of the present invention loads configuration data capable of processing an air interface or portion thereof in a wireless syst... | 02/28/2006 |
