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| Number | Title | Issue Date |
| 7376872 | Testing embedded memory in integrated circuits such as programmable logic devices Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIS... | 05/20/2008 |
| 7376917 | Client-server semiconductor verification system A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing a design of a logic circuit. A server is coupled to the client devic... | 05/20/2008 |
| 7376873 | Method and system for selectively masking test responses An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit. ... | 05/20/2008 |
| 7376874 | Method of controlling a test mode of a circuit A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other... | 05/20/2008 |
| 7373570 | LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits A scan separator in a large scale integration device is made more extensive to suppress an increase in the circuit scale of the entire device. In one embodiment, a scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks... | 05/13/2008 |
| 7373550 | Generation of a computer program to test for correct operation of a data processing apparatus Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to ... | 05/13/2008 |
| 7373565 | Start/stop circuit for performance counter A circuit for tracking a number of clock cycles between occurrences of an event of interest. The circuit includes logic for asserting a run signal responsive to a first occurrence of the event of interest, logic for deasserting the run signal responsive to a second ... | 05/13/2008 |
| 7373571 | Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automa... | 05/13/2008 |
| 7373637 | Method and apparatus for counting instruction and memory location ranges A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a co... | 05/13/2008 |
| 7373566 | Semiconductor device for accurate measurement of time parameters in operation A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit,which includes an input/output selector with test function. A test clock signal, which is directly supplied in the test mode, is used to selectively tak... | 05/13/2008 |
| 7372995 | Analysis apparatus An analysis apparatus includes an information acquisition part for acquiring shape information about an analysis target object, an additional information extraction part for extracting additional information on the analysis target object from the shape information, ... | 05/13/2008 |
| 7372752 | Test mode controller A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable t... | 05/13/2008 |
| 7373547 | Self-reparable semiconductor and method thereof A self-reparable semiconductor comprises first, second and spare functional units including first and second sub-functional units that cooperate to perform first and second functions. The first and second sub-functional units of the first, second and first spare fun... | 05/13/2008 |
| 7372288 | Test apparatus for testing multiple electronic devices There is disclosed a test apparatus including a driver that outputs a test signal, a first switch that is provided between the driver and a terminal of the first device under test, a second switch that is provided between the driver and a terminal of the second devi... | 05/13/2008 |
| 7372305 | Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch outpu... | 05/13/2008 |
| 7373572 | System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data ... | 05/13/2008 |
| 7373627 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) fo... | 05/13/2008 |
| 7373622 | Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed ar... | 05/13/2008 |
| 7373574 | Semiconductor testing apparatus and method of testing semiconductor A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison s... | 05/13/2008 |
| 7373623 | Method and apparatus for locating circuit deviations A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of... | 05/13/2008 |
| 7370256 | Integrated circuit testing module including data compression Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit a... | 05/06/2008 |
| 7370253 | Apparatus and method for high-speed SAS link protocol testing An apparatus for changing a connection between two serial components on the same circuit board. The apparatus comprises at least one column, and each column includes first, second, third and fourth pads. The first pad communicates with a first breakout connector dis... | 05/06/2008 |
| 7368931 | On-chip self test circuit and self test method for signal distortion There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load b... | 05/06/2008 |
| 7370247 | Dynamic offset compensation based on false transitions A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detec... | 05/06/2008 |
| 7369604 | Time correlation of data acquisition samples from independent systems in a logic analyzer Apparatus according to the subject invention includes two independent acquisition systems, wherein one of the two independent acquisition systems acquires the acquisition clock of the other acquisition system along with a signal from a known acquisition reference po... | 05/06/2008 |
| 7370237 | Semiconductor memory device capable of accessing all memory cells A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a tester having M channels, K ones of the N channels of the memory device... | 05/06/2008 |
| 7370257 | Test vehicle data analysis A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix for... | 05/06/2008 |
| 7366952 | Interconnect condition detection using test pattern in idle packets In some embodiments, a receiver can receive from an interconnect information packets and idle packets, where one or more of the idle packets includes a test pattern. A condition detector can detect a condition of the interconnect in response to the test pattern. Oth... | 04/29/2008 |
| 7366967 | Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pa... | 04/29/2008 |
| 7367001 | Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intend... | 04/29/2008 |
| 7365554 | Integrated circuit for determining a voltage An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage ge... | 04/29/2008 |
| 7366597 | Validating control system software variables A vehicle having a system for validating a variable signal for input to a processor-performed function. An input module receives the signal. A processor tests first and second storage locations of a memory. After testing, the processor stores the signal in the first... | 04/29/2008 |
| 7365565 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| RE40282 | Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily ... | 04/29/2008 |
| 7363501 | Semiconductor integrated circuit with function to manage license information A semiconductor integrated circuit includes one or more function blocks, a nonvolatile memory unit which stores therein coded license information, and a decoder circuit which decodes the license information stored in the nonvolatile memory unit, and makes one of the... | 04/22/2008 |
| 7363557 | System for at-speed automated testing of high serial pin count multiple gigabit per second devices A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holdi... | 04/22/2008 |
| 7363377 | Method for protecting the program environment of a microsoft component object model (COM) client An apparatus for and method of creating a standardized interface between Microsoft Component Object Model environment and a non-compatible legacy environment. The technique is equally effective for both object oriented and non-object oriented scripting protocols. Th... | 04/22/2008 |
| 7363402 | Data communications architecture employing parallel SERDES channels A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains var... | 04/22/2008 |
| 7363558 | Semiconductor device and method for testing the same A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to prov... | 04/22/2008 |
