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| Number | Title | Issue Date |
| 7519882 | Intelligent binning for electrically repairable semiconductor chips The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any.... | 04/14/2009 |
| 7516375 | Methods and systems for repairing an integrated circuit device Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defectiv... | 04/07/2009 |
| 7506228 | Measuring the internal clock speed of an integrated circuit A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchr... | 03/17/2009 |
| 7506229 | Method and system for optimizing an integrated circuit A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional mo... | 03/17/2009 |
| 7506227 | Integrated circuit with embedded identification code An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the pl... | 03/17/2009 |
| 7500161 | Correcting test system calibration and transforming device measurements when using multiple test fixtures A test system and methods using the test system correlate measurements of a device under test (DUT) regardless of which test fixture is used for in-fixture testing of the DUT. The test system includes test equipment, a test fixture that interfaces the DUT to the tes... | 03/03/2009 |
| 7496815 | Method and apparatus for automatic generation of system test libraries An apparatus and associated methodology are provided to generate system test libraries for solution testing involving heterogeneous devices from different vendors. A unified user interface employs received information to execute the tests based on provided device an... | 02/24/2009 |
| 7496812 | Apparatus and method for testing and debugging an integrated circuit An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer th... | 02/24/2009 |
| 7496813 | Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared integrated circuit pin 14. The functional signal and t... | 02/24/2009 |
| 7496814 | Load testing of a telecommunication network A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with the load test being divided into several test phases and on the graphi... | 02/24/2009 |
| 7493535 | JTAG circuit transferring data between devices on TCK terminals The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an ... | 02/17/2009 |
| 7487415 | Memory circuitry with data validation Memory circuitry is augmented with data validation circuitry that is closely coupled to the memory circuitry so that data read out of the memory for use in a validation operation does not have to pass through or to general-purpose routing or logic circuitry before i... | 02/03/2009 |
| 7484145 | Method for embedded integrated end-to-end testing A method and system for automated testing of a system such as a billing module in a telecommunication system is disclosed. In a first embodiment, test APIs, scenarios and configuration information are embedded into the module itself in a way such that, when testing ... | 01/27/2009 |
| 7484147 | Semiconductor integrated circuit A semiconductor integrated circuit for intentionally and flexibly changing a monitoring subject bit if debugging is performed during software processing when a status change occurs. A replacement data register and a comparison address register, which are settable fr... | 01/27/2009 |
| 7484146 | Method for capturing multiple data packets in a data signal for analysis A method for selectively capturing selected portions of multiple data packets within a packet data signal for analysis by capturing only desired or necessary portions of the data packets and assembling them into substantially contiguous data streams prior to transfe... | 01/27/2009 |
| 7480841 | Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal i... | 01/20/2009 |
| 7480840 | Apparatus, system, and method for facilitating port testing of a multi-port host adapter An apparatus, system, and method are provided for facilitating port testing of a multi-port host adapter. The present invention includes a scheduler that schedules execution of a plurality of threads to test a first port and a plurality of threads to test a second p... | 01/20/2009 |
| 7478293 | Method of securing the test mode of an integrated circuit via intrusion detection An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the mod... | 01/13/2009 |
| 7478294 | Time controllable sensing scheme for sense amplifier in memory IC test A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is iss... | 01/13/2009 |
| 7478295 | Method and apparatus of fault diagnosis for integrated logic circuits In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input signal lines and the output signal lines, different symbols are inje... | 01/13/2009 |
| 7475305 | Method of high speed data rate testing A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test sys... | 01/06/2009 |
| 7475302 | Decoded match circuit for performance counter A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected ... | 01/06/2009 |
| 7475303 | HyperJTAG system including debug probe, on-chip instrumentation, and protocol A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip ... | 01/06/2009 |
| 7475304 | Bit error tester A method and device for comparing two generic digital signals over a wide range of data rates and for counting the number of bit errors between digital signals under the conditions of noise and jamming. The bit error tester of the invention compares the digital sign... | 01/06/2009 |
| 7475301 | Increment/decrement circuit for performance counter An increment/decrement circuit for use with a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. In one embodiment, the increment/decrement circuit includes a delay circuit block operable to receive and align the debug data. Fir... | 01/06/2009 |
| 7472320 | Autonomous self-monitoring and corrective operation of an integrated circuit Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrat... | 12/30/2008 |
| 7472323 | Mechanism to stop instruction execution at a microprocessor A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop exec... | 12/30/2008 |
| 7472322 | On-chip interface trap characterization and monitoring A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply v... | 12/30/2008 |
| 7472321 | Test apparatus for mixed-signal semiconductor device A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture inclu... | 12/30/2008 |
| 7469370 | Enabling multiple testing devices A method for enabling multiple testing devices within a system. The method may include determining whether a first testing device or a second testing device is coupled to the system. Provided the first testing device is coupled to the system, the method may include ... | 12/23/2008 |
| 7467339 | Semiconductor integrated circuit and a method of testing the same A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a vo... | 12/16/2008 |
| 7467340 | TAP, ST, lockout, and IR SO enable output data control Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan... | 12/16/2008 |
| 7454674 | Digital jitter detector In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to... | 11/18/2008 |
| 7451368 | Semiconductor device and method for testing semiconductor device A packaged semiconductor device that enables testing of semiconductor chips incorporated therein in a simplified and efficient manner. The semiconductor device includes a packaged logic chip for processing data and a packaged memory chip for storing data that is pro... | 11/11/2008 |
| 7447959 | Semiconductor integrated circuit and a method of testing the same A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a vo... | 11/04/2008 |
| 7447958 | Parallel input/output self-test circuit and method A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” mu... | 11/04/2008 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7444570 | Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit g... | 10/28/2008 |
| 7444571 | Apparatus and method for testing and debugging an integrated circuit A system for testing a target integrated circuit comprises a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the integrated circuit and that analyzes received data from the target integrated circuit. A... | 10/28/2008 |
| 7444575 | Architecture and method for testing of an integrated circuit device In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test cir... | 10/28/2008 |
