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| Number | Title | Issue Date |
| 7343558 | Configurable automatic-test-equipment system A method and system for measuring a device under test includes connecting a first test instrument and a second test instrument to a programmable logic device. The programmable logic device is configured to comply with interface specifications of the first test instr... | 03/11/2008 |
| 7342409 | System for testing semiconductor components A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconn... | 03/11/2008 |
| 7342603 | Image output test system and method and device thereof The present invention is to provide an image output test system, which is built in between an image output device and an image output test device, in which the image output test device can receive a first video signal, convert the first video signal into a second vi... | 03/11/2008 |
| 7343279 | Universal approach for simulating, emulating, and testing a variety of serial bus types An electronic apparatus for testing equipment for serial busses employs a generic bus model that breaks down a serial bus into separate layers that are managed by separate processors. The processors have parameters that can be programmed for communicating via one ty... | 03/11/2008 |
| 7343480 | Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the... | 03/11/2008 |
| 7343535 | Embedded testing capability for integrated serializer/deserializers Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional... | 03/11/2008 |
| 7343538 | Programmable multi-function module for automatic test equipment systems A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement ca... | 03/11/2008 |
| 7340698 | Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly coup... | 03/04/2008 |
| 7340657 | On-chip high-speed serial data analyzers, systems, and associated methods In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined vo... | 03/04/2008 |
| 7340707 | Automatic tuning of signal timing A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay ... | 03/04/2008 |
| 7340359 | Augmenting semiconductor's devices quality and reliability A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and ot... | 03/04/2008 |
| 7340364 | Test apparatus, and control method There is provided a test apparatus that tests a device under test. The test apparatus includes a control processor that executes a test program for testing the device under test, a test unit that is connected to the device under test and tests the device under test ... | 03/04/2008 |
| 7340352 | Inspecting method, inspecting apparatus, and method of manufacturing semiconductor device An inspecting method is capable of efficiently inspecting a wafer. According to the inspecting method, the chip area of a wafer is inspected for defects, and based on the results, a defect density D0p of each of peripheral-zone chips in the chip area whic... | 03/04/2008 |
| 7340644 | Self-reparable semiconductor and method thereof A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a def... | 03/04/2008 |
| 7340656 | Method and apparatus for probing a computer bus The subject invention facilitates the efficient operation of the disassembly of the microprocessor bus by providing an apparatus and method for detecting and correcting a strobe phase inversion and predrive filtering in a 2× source synchronous data transfer bus. Ap... | 03/04/2008 |
| 7339388 | Intra-clip power and test signal generation for use with test structures on wafers The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performa... | 03/04/2008 |
| 7339772 | Hot-swap protection circuit Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-faul... | 03/04/2008 |
| 7337376 | Method and system of self-test for a single infrared machine A system and method of self-test for a single infrared machine. An infrared transimit circuit may be set up succesfully by only using a host with an external infrared module without a use of another test machine. A test procedure is excuted through the infrared tran... | 02/26/2008 |
| 7337378 | Semiconductor integrated circuit and burn-in test method thereof To provide a semiconductor integrated circuit that includes a flash EEPROM on which an efficient burn-in test can be carried out and a burn-in test method thereof. By changing the level of a control signal C1 from the mode selecting unit 40, the operat... | 02/26/2008 |
| 7337366 | Microcomputer, a method for protecting memory and a method for performing debugging A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not t... | 02/26/2008 |
| 7337088 | Intelligent measurement modular semiconductor parametric test system An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate with a user via a user interface, and is further operable to communicate with and to control the state of... | 02/26/2008 |
| 7337305 | Method and pipeline architecture for processing multiple swap requests to reduce latency A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the pipeline immediately following the first swap request. The first swap ... | 02/26/2008 |
| 7337379 | Apparatus and method for diagnosing integrated circuit An apparatus being able to not only detect a manufacturing defect of an integrated circuit but also specify a position at which the defect occurs even when outputs from scan paths are compressed and stored, or when the number of the scan paths is large. The apparatu... | 02/26/2008 |
| 7337380 | Eye width characterization mechanism An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from the pass setting until the sampling phase is outside the eye width of t... | 02/26/2008 |
| 7336749 | Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique ... | 02/26/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7332938 | Domino logic testing systems and methods A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance w... | 02/19/2008 |
| 7334060 | System and method for increasing the speed of serially inputting data into a JTAG-compliant device A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made the active instruction, extending the capability of the test access p... | 02/19/2008 |
| 7334171 | Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into t... | 02/19/2008 |
| 7334174 | Semiconductor integrated circuit device and error detecting method therefor A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses informati... | 02/19/2008 |
| 7332929 | Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in th... | 02/19/2008 |
| 7330024 | Power supply device, test apparatus, and power supply voltage stabilizing device A power supply device for supplying source current to an electronic device comprises: a current output unit for outputting output current including at least the source current as a component of the current thereof; a connection resistor which electrically connects t... | 02/12/2008 |
| 7330066 | Reference voltage generation circuit that generates gamma voltages for liquid crystal displays A gamma voltage generation circuit coupled to a digital-to-analog converter and provides the digital-to-analog converter with reference voltages by voltage division through resistor circuits. A variable voltage source can be modulated and charge-sharing switches can... | 02/12/2008 |
| 7330514 | Methods and apparatus to mitigate cross-talk interference A circuit board includes a pair of interconnects configured to support conveyance of a differential mode communication signal, which comprises a balanced first signal (e.g., signal X) and corresponding second signal (e.g., signal −X) of opposite polarities. A tran... | 02/12/2008 |
| 7331003 | Match circuit for performance counter In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit por... | 02/12/2008 |
| 7330044 | Method and apparatus for semiconductor testing A semiconductor testing system including an input; a display; multiple testing units; a memory in which is stored multiple applications that specify the operating procedure of the testing units and multiple categories that are related to the applications; and a cont... | 02/12/2008 |
| 7330809 | Trace data compression system and trace data compression method and microcomputer implemented with a built-in trace data compression circuit A trace data compression system includes a data acquisition circuit which is configured to acquire address information for identifying an address for reading or writing operation of a microcomputer which performs predetermined processing, and data information as ope... | 02/12/2008 |
| 7328375 | Pass through debug port on a high speed asynchronous link An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge dev... | 02/05/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7328383 | Circuit and method for testing embedded phase-locked loop circuit In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock... | 02/05/2008 |
