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| Number | Title | Issue Date |
| 8185863 | Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information ex... | 05/22/2012 |
| 8161335 | System and method for testing a circuit A system for testing a circuit. The system comprises a first circuit mounted on an embedded first circuit board and a test circuit mounted on the embedded first circuit board. The system further comprises a second circuit board on the first circuit board, the second... | 04/17/2012 |
| 8161336 | Apparatus and method for testing and debugging an integrated circuit A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JT... | 04/17/2012 |
| 8151151 | Tap time division multiplexing with scan test An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testa... | 04/03/2012 |
| 8145961 | Fast ECC memory testing by software including ECC check byte The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or mu... | 03/27/2012 |
| 8140922 | Method for correlating an error message from a PCI express endpoint In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of th... | 03/20/2012 |
| 8136001 | Technique for initializing data and instructions for core functional pattern generation in multi-core processor Techniques have been developed to introduce processor core functional pattern tests into a memory space addressable by at least one processor core of an integrated circuit. In general, such functional pattern tests can include both instruction sequences and data pat... | 03/13/2012 |
| 8136002 | Communication between controller and addressed target devices over data signal An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning ci... | 03/13/2012 |
| 8122309 | Method and apparatus for processing failures during semiconductor device testing Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first ... | 02/21/2012 |
| 8103923 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is c... | 01/24/2012 |
| 8086921 | System and method of clocking an IP core during a debugging operation According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source. ... | 12/27/2011 |
| 8086920 | Method of controlling a test mode of a circuit A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other... | 12/27/2011 |
| 8078924 | Method and system for generating a global test plan and identifying test requirements in a storage system environment The present invention is directed to a system and method for a quality assurance tool generating test plans and identifying new test requirements for a new version of a product. Old versions of the product may be previously tested and test plan documents associated ... | 12/13/2011 |
| 8074131 | Generic debug external connection (GDXC) for high integration integrated circuits A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proxima... | 12/06/2011 |
| 8065651 | Implementing hierarchical design-for-test logic for modular circuit design Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry ... | 11/22/2011 |
| 8051345 | Method and apparatus for securing digital information on an integrated circuit during test operating modes The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC in... | 11/01/2011 |
| 8051403 | Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information ex... | 11/01/2011 |
| 8051346 | Fault injection Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data... | 11/01/2011 |
| 8046647 | TAP sampling at double rate An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge. ... | 10/25/2011 |
| 8042073 | Sorted data outlier identification Embodiments of the present invention provide for sorted data signature analysis for identifying outliers in datasets. Some embodiments disclose a nearest pattern smallest delta procedure to identify outliers in a dataset of vector patterns. Other embodiments disclos... | 10/18/2011 |
| 8042014 | Semiconductor apparatus and method of disposing observation flip-flop A semiconductor apparatus includes a functional block to observe a state of a signal line in the apparatus. The functional block includes a signal transfer section to receive, transmit and output the state of the signal line, and an observation flip-flop to store a ... | 10/18/2011 |
| 8042086 | Method and apparatus for verifying integrated circuit design using a constrained random test bench A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly sele... | 10/18/2011 |
| 8037089 | Test system A test system for testing a plurality of devices under test is disclosed. The test system includes a tester and a plurality of processors. The tester is used for providing a plurality of control signals and determining a plurality of test results for the devices und... | 10/11/2011 |
| 8032805 | Input-output device testing including voltage tests Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, ... | 10/04/2011 |
| 8028208 | Wireless radio frequency technique design and method for testing of integrated circuits and wafers Various embodiments are described herein for an apparatus and method for the wireless testing of Integrated Circuits and wafers. In one embodiment, the apparatus comprises a test unit external from the wafer and at least one test circuit that is fabricated on the wa... | 09/27/2011 |
| 8015514 | Random personalization of chips during fabrication Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to random... | 09/06/2011 |
| 8010855 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit A semiconductor device is capable of being coupled to first and second debuggers, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to th... | 08/30/2011 |
| 8006148 | Test mode control circuit and method for using the same in semiconductor memory device A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of... | 08/23/2011 |
| 7987397 | Testing mobile wireless devices during device production A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/... | 07/26/2011 |
| 7982483 | Circuit and method for component communication A circuit has a supply voltage terminal for receiving a supply voltage of the circuit, wherein a trigger impulse is superimposed on the supply voltage. Further, the circuit has a signal terminal for outputting an output signal voltage of the circuit, wherein a bit o... | 07/19/2011 |
| 7984346 | Integrated apparatus for testing image devices An integrated apparatus for testing image devices is disclosed, in which a plurality of testing apparatuses needed when an image-related device is installed are integrated into one construction for thereby achieving a good portability as compared to a conventional a... | 07/19/2011 |
| 7966533 | Register device and methods for using such Various systems and methods for registering data are disclosed herein. For example, test enabled flip-flop devices are provided. Such devices include a test mode input signal and a register output signal. In addition, the devices include a flip-flop with a data inpu... | 06/21/2011 |
| 7949914 | Diagnostic mode switching A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic ... | 05/24/2011 |
| 7945828 | Integrated circuit arrangement and design method An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode... | 05/17/2011 |
| 7945827 | Method and device for scan chain management of dies reused in a multi-chip package An apparatus and method for economical testing of dies in a multichip module. Internal I/O pins on a die are logically connected to external I/O pins of the multichip module through the use of a silicon interposer on which the dies are attached. Multiplexers on the ... | 05/17/2011 |
| 7941715 | Asynchronous set-reset circuit device An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The log... | 05/10/2011 |
| 7930604 | Apparatus and method for testing and debugging an integrated circuit A system for receiving serial messages from a device under test includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) dat... | 04/19/2011 |
| 7930603 | Feature-oriented test program development and execution A resource constraint management unit for a target test system is described. The resource constraint management unit has an interface adapted for receiving, together with a test program, feature specifications for at least one test of the test program, said feature ... | 04/19/2011 |
| 7921344 | Multi-stage data processor with signal repeater A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing ... | 04/05/2011 |
| 7921343 | Testing system, testing system control method, and test apparatus A testing system including a plurality of test applying portions that operate a test device for outputting an output signal; a plurality of testing portions that test the output signal of the test device; and a switch portion that switches the output signal between ... | 04/05/2011 |
