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| Number | Title | Issue Date |
| 8117509 | Memory control circuit, semiconductor integrated circuit, and verification method of nonvolatile memory A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the... | 02/14/2012 |
| 8117490 | Microprocessor memory management A memory for an electronic brake control system is divided into portions that are classified as critical and non-critical. Each portion is periodically tested for faults. Upon detection of a fault, the memory is reconfigured with any operations of the brake system a... | 02/14/2012 |
| 8112682 | Method and device for bad-block testing Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing ... | 02/07/2012 |
| 8108739 | High-speed testing of integrated devices A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device wit... | 01/31/2012 |
| 8108740 | Method for operating a memory device In the method for operating a memory device which has a number of memory blocks, the memory blocks are marked as intact, suspect, or defective. The memory blocks marked as suspect are monitored. If the number of memory blocks marked as intact in the memory device fa... | 01/31/2012 |
| 8103919 | Circuit for and method of repairing defective memory A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for ... | 01/24/2012 |
| 8103920 | Memory system configured by using a nonvolatile semiconductor memory A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein ... | 01/24/2012 |
| 8103921 | Fully-buffered dual in-line memory module with fault correction A memory system including a first memory, a content addressable memory, a testing module, and a memory controller. The first memory includes first memory cells. The content addressable memory includes second memory cells and is configured to store addresses of selec... | 01/24/2012 |
| 8103918 | Clock control during self-test of multi port memory A multiport memory is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be us... | 01/24/2012 |
| 8099639 | Failure analysis method, failure analysis system, and memory macro system Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare ce... | 01/17/2012 |
| 8099638 | Apparatus and methods for tuning a memory interface The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory ... | 01/17/2012 |
| 8095835 | Error scanning in flash memory Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write opera... | 01/10/2012 |
| 8095834 | Macro and command execution from memory array Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. M... | 01/10/2012 |
| 8090999 | Memory media characterization for development of signal processors Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs. Models are developed from capturing output of memory devices of the type utilizing analog signals to communi... | 01/03/2012 |
| 8085056 | Circuit for testing internal voltage of semiconductor memory apparatus An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting un... | 12/27/2011 |
| 8086917 | Methods for characterizing device variation in electronic memory circuits A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage grea... | 12/27/2011 |
| 8086916 | System and method for running test and redundancy analysis in parallel A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs f... | 12/27/2011 |
| 8074129 | Memory apparatus and method and reduced pin count apparatus and method A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-... | 12/06/2011 |
| 8069380 | Method, system and computer-readable code to test flash memory A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the fla... | 11/29/2011 |
| 8069379 | Memory system with point-to-point request interconnect A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory de... | 11/29/2011 |
| 8065572 | At-speed scan testing of memory arrays An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a mem... | 11/22/2011 |
| 8060799 | Hub, memory module, memory system and methods for reading and writing to the same A hub, a memory module, a memory system, and methods for reading and writing to the same. In a test mode, memory module, memory device or memory unit identifying information may be ignored, so that all memory modules, memory devices or memory units may be test writt... | 11/15/2011 |
| 8055959 | Disabling faulty flash memory dies Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the... | 11/08/2011 |
| 8051343 | Method of testing a memory module and hub of the memory module Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wher... | 11/01/2011 |
| 8051344 | Semiconductor memory testing device and method of testing semiconductor using the same The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. ... | 11/01/2011 |
| 8051341 | Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applie... | 11/01/2011 |
| 8051342 | Semiconductor memory device A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality ... | 11/01/2011 |
| 8046643 | Transport subsystem for an MBIST chain architecture An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plur... | 10/25/2011 |
| 8046644 | DRAM testing method A method for testing a dynamic random access memory (DRAM) includes copying a test program from the DRAM to a random access memory (RAM). Start and end physical addresses of the DRAM are respectively stored in first and second registers. First test data is written t... | 10/25/2011 |
| 8042012 | Systems and devices including memory with built-in self test and methods of making and using the same Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switc... | 10/18/2011 |
| 8042011 | Runtime programmable BIST for testing a multi-port memory device One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single p... | 10/18/2011 |
| 8037380 | Verifying data integrity of a non-volatile memory system during data caching process To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the... | 10/11/2011 |
| 8037379 | Prediction of impact on post-repair yield resulting from manufacturing process modification A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data representing locations of defective memory cells for a plurality of memory devices. The bit data is modified... | 10/11/2011 |
| 8037378 | Automatic test entry termination in a memory device A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, t... | 10/11/2011 |
| 8028207 | Early memory test A PC BIOS can contain an early memory test that can identify a memory slot containing a bad memory. The BIOS can also contain a program module for using a communications port to report the identified memory slot. The communications port used for reporting is one tha... | 09/27/2011 |
| 8024628 | Apparatus and method for testing semiconductor memory device A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operat... | 09/20/2011 |
| 8024629 | Input/output compression and pin reduction in an integrated circuit An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting se... | 09/20/2011 |
| 8024627 | Semiconductor memory device, operating method thereof, and compression test method thereof A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compr... | 09/20/2011 |
| 8020056 | Memory channel with bit lane fail-over Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plura... | 09/13/2011 |
| 8020055 | Method and apparatus for testing the connectivity of a flash memory chip In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, th... | 09/13/2011 |
