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| Number | Title | Issue Date |
| 8443243 | Semiconductor integrated circuit device and method for evaluating an eye-opening margin An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration... | 05/14/2013 |
| 8392767 | Data channel test apparatus and method thereof A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device ar... | 03/05/2013 |
| 8370787 | Testing security of mapping functions Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests... | 02/05/2013 |
| 8327196 | Identifying an optimized test bit pattern for analyzing electrical communications channel topologies Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked chann... | 12/04/2012 |
| 8209571 | Valid-transmission verifying circuit and a semiconductor device including the same A valid-transmission verifying circuit and a semiconductor device including the same are provided. The valid-transmission verifying circuit provides data to an output circuit in correspondence with reference data, the valid-transmission verifying circuit comprising:... | 06/26/2012 |
| 8069378 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 11/29/2011 |
| 8065571 | Storage area network (SAN) link integrity tester A tester that generates various data patterns to assure that link receivers and transmitters are functioning properly (i.e., are functioning according to a relevant network specification) across the entire storage area network. In various embodiments, this tester ma... | 11/22/2011 |
| 7979756 | Apparatus, system and method for a go/no go link integrity tester An apparatus, system and method for a go/no go tester that uses various data patterns to assure that equipments, systems and networks using data links, receivers and transmitters are working within the range of predetermined requirements of standards, specifications... | 07/12/2011 |
| 7958408 | On-chip receiver sensitivity test mechanism An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation ca... | 06/07/2011 |
| 7934132 | Communication system and method for controlling the same For an error rate QBER, threshold values are preset, including a threshold value Qbit for frame synchronization processing, a threshold value Qphase for phase correction processing, and a threshold value QEve for eavesdropping detect... | 04/26/2011 |
| 7913128 | Data channel test apparatus and method thereof A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device ar... | 03/22/2011 |
| 7908528 | Phase-detector-less method and apparatus for minimizing skew between bonded channel groups A method for aligning output from a first transmit source and a second transmit source is provided. The method includes combining complementary portions of differential signals generated from respective transmit sources to generate an output bit sequence and compari... | 03/15/2011 |
| 7890821 | Channel impairment emulator systems and methods Systems and methods are disclosed herein to provide improved communication system test techniques. For example, in accordance with an embodiment of the present invention, a wireless device test system is disclosed having a channel emulator for multipath and/or MIMO ... | 02/15/2011 |
| 7877648 | Fault tolerant data processing A method of identifying a valid version of a data value and voting on separate instances of the data value is described. A processor receives an instance of the data value generated by one processor and a transmitted version of that generated instance transmitted by... | 01/25/2011 |
| 7788552 | Method to improve isolation of an open net fault in an interposer mounted module A multi-chip module (MCM) assembly has two modules interconnected by respective interposers and a printed circuit board, and diagnostic logic within the modules uses the principal of signal reflection to located any open fault in the circuit path across the interpos... | 08/31/2010 |
| 7779313 | Testing apparatus and testing method Provided is test apparatus with higher testing efficiency, including: plurality of pattern generating sections generating test pattern to supply to devices under test; group control section controlling group of pattern generating sections out of the pattern generati... | 08/17/2010 |
| 7770078 | Integrated circuit communication self-testing An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-... | 08/03/2010 |
| 7739561 | Method and apparatus for monitoring an optical network signal A method is disclosed for monitoring a communication link between a first apparatus and a second apparatus, the method comprising receiving concurrently from the first apparatus (e.g., a central office) at the second apparatus (e.g., an optical demarcation point at ... | 06/15/2010 |
| 7721164 | Method and apparatus for improved storage area network link integrity testing A method and apparatus that is configured to issue an echo extended link service with a payload of data patterns that are known in the art of fiber channel to produce jitter. The inventive apparatus is configured to use an echo extended link service to send data wit... | 05/18/2010 |
| 7685479 | Telecommunications network testing On a test apparatus for a telecommunication network a plurality of quality rules are defined as a function of the results of counts of events for a plurality of test parameters. The events relating to the plurality of test parameters during the performance of a test... | 03/23/2010 |
| 7669093 | Information radio transmission system An information radio transmission system is provided that enables provision of correct control information on the transmitting side irrespective of the error volume when an error occurs in communication data. Error volume measuring data string storage units that sto... | 02/23/2010 |
| 7493532 | Methods and structure for optimizing SAS domain link quality and performance Methods and structures within a SAS domain for automated tuning performance of a coupled pair of transceivers. In one aspect hereof, control registers of a transmitting transceiver coupled to a receiving transceiver are adjusted to a plurality of distinct combinatio... | 02/17/2009 |
| 7490275 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 02/10/2009 |
| 7480839 | Qualified anomaly detection A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detecte... | 01/20/2009 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7437643 | Automated BIST execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is p... | 10/14/2008 |
| 7434118 | Parameterized signal conditioning A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one ter... | 10/07/2008 |
| 7434114 | Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training se... | 10/07/2008 |
| 7426599 | Systems and methods for writing data with a FIFO interface Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I... | 09/16/2008 |
| 7405723 | Apparatus for testing display device and method for testing the same An apparatus for testing a display device includes a display device to display test patterns, a graphic process unit to supply analog mode signals and digital mode signals to the display device, and a control unit to allow test patterns of an analog testing mode and... | 07/29/2008 |
| 7404114 | System and method for balancing delay of signal communication paths through well voltage adjustment A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A r... | 07/22/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7395466 | Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag... | 07/01/2008 |
| 7386767 | Programmable bit error rate monitor for serial interface A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag ge... | 06/10/2008 |
| 7380152 | Daisy chained multi-device system and operating method A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the dais... | 05/27/2008 |
| 7373561 | Integrated packet bit error rate tester for 10G SERDES An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and ... | 05/13/2008 |
| 7373577 | CAN system Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error d... | 05/13/2008 |
| 7366952 | Interconnect condition detection using test pattern in idle packets In some embodiments, a receiver can receive from an interconnect information packets and idle packets, where one or more of the idle packets includes a test pattern. A condition detector can detect a condition of the interconnect in response to the test pattern. Oth... | 04/29/2008 |
| 7360127 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 04/15/2008 |
| 7355416 | Measurement of cable quality by power over ethernet A method of determining impedance comprising: supplying power to a powered device from a power sourcing equipment at a first current limited level, Ilim1; measuring, at a plurality of times a voltage associated with the output of the power sourcing equipm... | 04/08/2008 |
