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| Number | Title | Issue Date |
| 8190950 | Dynamic column redundancy replacement A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latche... | 05/29/2012 |
| 8069377 | Integrated circuit having memory array including ECC and column redundancy and method of operating the same An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, multiplexer circuitry, coupled to the memory... | 11/29/2011 |
| 8037376 | On-chip failure analysis circuit and on-chip failure analysis method An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure detection unit which detects a failure of the output of the memory, a fail data storage unit in which fail da... | 10/11/2011 |
| 7941712 | Method for error test, recordation and repair In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a com... | 05/10/2011 |
| 7908527 | Semiconductor integrated circuit and redundancy method thereof A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information the... | 03/15/2011 |
| 7836362 | Circuits and methods for repairing defects in memory devices Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory seg... | 11/16/2010 |
| 7788551 | System and method for repairing a memory A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-t... | 08/31/2010 |
| 7788550 | Redundant bit patterns for column defects coding Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective... | 08/31/2010 |
| 7783941 | Memory devices with error detection using read/write comparisons A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code resp... | 08/24/2010 |
| 7779312 | Built-in redundancy analyzer and method for redundancy analysis A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault mem... | 08/17/2010 |
| 7774660 | Flexible row redundancy system A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row f... | 08/10/2010 |
| 7702972 | Method and apparatus for SRAM macro sparing in computer chips SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM ma... | 04/20/2010 |
| 7698608 | Using a single bank of efuses to successively store testing data from multiple stages of testing A mechanism is provided for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch o... | 04/13/2010 |
| 7647536 | Repair bits for a low voltage cache A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair modu... | 01/12/2010 |
| 7634695 | Test apparatus and selection apparatus There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns. The test apparatus includes a testing section, a flag memory that stores thereon a flag indicating whether each column i... | 12/15/2009 |
| 7600165 | Error control coding method and system for non-volatile memory Methods and systems for improving repairing efficiency in non-volatile memory. Repairing data may be read from an information array associated with the non-volatile memory. The repairing data is generally read to a volatile latch associated with the non-volatile mem... | 10/06/2009 |
| 7437627 | Method and test device for determining a repair solution for a memory module Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, where... | 10/14/2008 |
| 7415640 | Methods and apparatuses that reduce the size of a repair data container for repairable memories Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to ex... | 08/19/2008 |
| 7415641 | System and method for repairing a memory A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-t... | 08/19/2008 |
| 7406620 | System and method for compiling a memory assembly with redundancy implementation In one embodiment, a computer-implemented system for compiling a fuse assembly for a memory is disclosed. The claimed embodiment comprises: means for defining a memory group including at least one memory instance, each memory instance being characterized by its memo... | 07/29/2008 |
| 7404113 | Flexible row redundancy system A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row f... | 07/22/2008 |
| 7395465 | Memory array repair where repair logic cannot operate at same operating condition as array Memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot... | 07/01/2008 |
| 7389451 | Memory redundancy with programmable control A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuit... | 06/17/2008 |
| 7383475 | Design structure for memory array repair where repair logic cannot operate at same operating condition as array Design structure for memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for th... | 06/03/2008 |
| 7380180 | Method, system, and apparatus for tracking defective cache lines To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information rega... | 05/27/2008 |
| 7373573 | Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch o... | 05/13/2008 |
| 7366946 | ROM redundancy in ROM embedded DRAM Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can als... | 04/29/2008 |
| 7360143 | Redundant storage of computer data Redundant storage of computer data including encoding N data values through M linear expressions into M encoded data values and storing each encoded data value separately on one of M redundant storage devices where M is greater than N and none of the linear expressi... | 04/15/2008 |
| 7355910 | Semiconductor memory device with shift redundancy circuits A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circu... | 04/08/2008 |
| 7352639 | Method and apparatus for increasing yield in a memory circuit Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the first mode, the control circuitry is operative to apply a first sign... | 04/01/2008 |
| 7352638 | Method and apparatus for testing a memory device The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that... | 04/01/2008 |
| 7350119 | Compressed encoding for repair A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarch... | 03/25/2008 |
| 7348820 | Method and apparatus for glitch-free control of a delay-locked loop in a network device A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals i... | 03/25/2008 |
| 7340558 | Multisection memory bank system A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area netwo... | 03/04/2008 |
| 7330379 | Semiconductor memory device having forced fail function of forcing a memory cell at a specific address to fail and method for testing same A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuit 21 which forcefully c... | 02/12/2008 |
| 7328379 | Look-up table for use with redundant memory A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuit... | 02/05/2008 |
| 7318175 | Memory modeling circuit with fault toleration A memory modeling circuit with fault toleration includes a compare circuit, a control circuit and a test circuit. The compare circuit receives the data stored in the same address of memories and compares data with each other to produce the correct reading data. The ... | 01/08/2008 |
| 7315479 | Redundant memory incorporating serially-connected relief information storage A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in seri... | 01/01/2008 |
| 7304900 | Semiconductor memory In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing ... | 12/04/2007 |
| 7305607 | Nonvolatile ferroelectric memory device including failed cell correcting circuit A nonvolatile ferroelectric memory device including a failed cell correcting circuit which effectively processes randomly distributed cell data. The nonvolatile ferroelectric memory device checks horizontal parity of a main memory cell array and stores the parity in... | 12/04/2007 |
