Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 8145957 | Using fractional sectors for mapping defects in disk drives Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Fu... | 03/27/2012 |
| 8132061 | Repair bits for a low voltage cache A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair modu... | 03/06/2012 |
| 8122304 | JTAG controlled self-repair after packaging An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to ... | 02/21/2012 |
| 8122303 | Data structure for flash memory and data reading/writing method thereof A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential ... | 02/21/2012 |
| 8112681 | Method and apparatus for handling fuse data for repairing faulty elements within an IC The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data ... | 02/07/2012 |
| 8095832 | Method for repairing memory and system thereof A method for repairing a main memory comprises the steps of: utilizing a spare memory to repair a main memory, wherein the spare memory includes a plurality of spare memory units; allocating a spare memory unit; determining whether available permutations of the allo... | 01/10/2012 |
| 8090998 | Method and apparatus for managing disc defects using updateable DMA, and disc thereof A disc defect management method and apparatus using a defect management area that can be updated, and a write once disc incorporating the method. A data area is disposed between a lead-in area and a lead-out area. The disc includes a defect management area (DMA) tha... | 01/03/2012 |
| 8086914 | Storing data to multi-chip low-latency random read memory device using non-aligned striping Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memo... | 12/27/2011 |
| 8086913 | Methods, apparatus, and systems to repair memory Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag ... | 12/27/2011 |
| 8074128 | Block management and replacement method, flash memory storage system and controller using the same A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped... | 12/06/2011 |
| 8060798 | Refresh of non-volatile memory cells based on fatigue conditions In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of ... | 11/15/2011 |
| 8055957 | Semiconductor integrated circuit device having fail-safe mode and memory control method An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, wh... | 11/08/2011 |
| 8055956 | Built-in self-repairable memory The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number... | 11/08/2011 |
| 8055958 | Replacement data storage circuit storing address of defective memory cell A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells ar... | 11/08/2011 |
| 8051339 | Data preserving method and data accessing method for non-volatile memory A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater ... | 11/01/2011 |
| 8046642 | TCAM BIST with redundancy A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spa... | 10/25/2011 |
| 8024626 | Automation of fuse compression for an ASIC design system A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The def... | 09/20/2011 |
| 8015457 | Redundancy circuit and semiconductor memory device Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant ... | 09/06/2011 |
| 8006143 | Semiconductor memory device and semiconductor memory device test method A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes de... | 08/23/2011 |
| 7992057 | Write-once type optical disc, and method and apparatus for managing defective areas on write-once type optical disc A recording medium and a method and apparatus for managing a defective area on the recording medium are provided. The method includes detecting an existence of a defective area within the data area of the recording medium; replacing the defective area with a replace... | 08/02/2011 |
| 7979755 | Semiconductor integrated circuit device for display controller The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area... | 07/12/2011 |
| 7962807 | Semiconductor storage apparatus managing system, semiconductor storage apparatus, host apparatus, program and method of managing semiconductor storage apparatus It is an object to provide a semiconductor storage apparatus managing system for implementing a semiconductor storage apparatus which can be actually utilized in place of a hard disk apparatus. A semiconductor storage apparatus managing system SY for managing... | 06/14/2011 |
| 7949908 | Memory repair system and method A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element in... | 05/24/2011 |
| 7945822 | Storing data to multi-chip low-latency random read memory device using non-aligned striping Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memo... | 05/17/2011 |
| 7937628 | Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redunda... | 05/03/2011 |
| 7913125 | BISR mode to test the redundant elements and regular functional memory to avoid test escapes A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is us... | 03/22/2011 |
| 7913126 | Semiconductor memory device and method of testing same Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. The memory device includes a logic circuit for outputting an activated redundant hit signal whe... | 03/22/2011 |
| 7895482 | Embedded memory repair A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive stat... | 02/22/2011 |
| 7890819 | Method and apparatus for storing failing part locations in a module A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module, such as data query (“DQ”) terminals, identified during a testing procedure. After testing, the non-v... | 02/15/2011 |
| 7890820 | Semiconductor test system with self-inspection of memory repair analysis A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit... | 02/15/2011 |
| 7873882 | Circuits and methods for repairing defects in memory devices Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory seg... | 01/18/2011 |
| 7853838 | Method and apparatus for handling failure in address line An address line failure handling apparatus includes a failed address line specifying unit that examines the address line connected to each bit and specifies a failed address line, an address line substituting unit in which an upper address line connected to an upper... | 12/14/2010 |
| 7849372 | Write-once recording medium and defective area management method and apparatus for write-once recording medium A method, apparatus and recording medium for managing defects are discussed. According to an embodiment, the method includes allocating at least one spare area to the recording medium, and at least one temporary defect management area to the spare area when a plural... | 12/07/2010 |
| 7840860 | Double DRAM bit steering for multiple error corrections A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determinat... | 11/23/2010 |
| 7831870 | JTAG controlled self-repair after packaging An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to ... | 11/09/2010 |
| 7818637 | Apparatus for formatting information storage medium An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data o... | 10/19/2010 |
| 7818636 | Method and apparatus for improving memory operation and yield A memory circuit comprises a first memory that stores data in a plurality of memory locations that are associated with memory addresses. A memory interface communicates with said first memory. A second memory communicates with said memory interface and stores memory... | 10/19/2010 |
| 7802152 | Method and apparatus for recording high-speed input data into a matrix of memory devices For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory de... | 09/21/2010 |
| 7797591 | Semiconductor integrated circuit, design support software system, and automatic test pattern generation system A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypas... | 09/14/2010 |
| 7793173 | Efficient memory product for test and soft repair of SRAM with redundancy Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant e... | 09/07/2010 |
