Class 714/709 - Data pulse evaluation/bit decision

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter in which the information bearing parameter
No. of patents: 169
Last issue date: 02/22/2011

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Number	Title	Issue Date
7895481	Multi-threshold channel equalization A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value rec...	02/22/2011
7886204	Methods of cell population distribution assisted read margining A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified...	02/08/2011
7734963	Non-causal channel equalization system A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value rec...	06/08/2010
7716538	Memory with cell population distribution assisted read margining A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified...	05/11/2010
7624312	System, apparatus, computer program product for performing operational validation with limited CPU use of a communications network A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is re...	11/24/2009
7549095	Error detection enhancement in a microprocessor through the use of a second dependency matrix A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector...	06/16/2009
7487411	Multi symbol bit detection for SDPSK signals This invention discloses a method of accurately detecting the current bit in a SDPSK modulated signal at the receiver. The proposed method calculates the current bit from the past-detected bits and the past symbols. Each past symbol estimates the current bit. Each o...	02/03/2009
7469367	Phase error determination method and digital phase-locked loop system In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel c...	12/23/2008
7434114	Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training se...	10/07/2008
7424656	Clocking methodology for at-speed testing of scan circuits with synchronous clocks A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element i...	09/09/2008
7424651	Method and apparatus for decision threshold control in an optical signal receiver An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and...	09/09/2008
7424230	Digital transmission system This digital transmission system is provided with a transmitting apparatus that transmits digital data signals and a receiving apparatus that receives the digital data signals transmitted over a transmission path, compares the signals with a predetermined threshold ...	09/09/2008
7404115	Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator...	07/22/2008
7395475	Circuit and method for fuse disposing in a semiconductor memory device A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode i...	07/01/2008
7392441	Method of performing operational validation with limited CPU use of a communications network A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is re...	06/24/2008
7392440	Optical reception device and optical reception method An optical signal receiving equipment including an optical-electrical converter configured to convert optical signals into electronic signals; first deciders configured to transform the electronic signals into first binary signals; a second decider configured to tra...	06/24/2008
7389455	Register file initialization to prevent unknown outputs during test A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a curr...	06/17/2008
7372802	Message communication via channels having strong fading In a transmitting/receiving concept a redundancy-adding encoder is used in order to obtain two data streams for different transmitters. In the receiver, the receiving signal is sampled by a first sampler synchronous to the first transmitter and is output by a second...	05/13/2008
7373577	CAN system Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error d...	05/13/2008
7370247	Dynamic offset compensation based on false transitions A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detec...	05/06/2008
7363553	System and method for adjusting soft decision thresholds in a soft-decision error correction system The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may be used to optimize threshold values by maximizing the mutual informa...	04/22/2008
7349552	Connected audio and other media objects Media objects are transformed into active, connected objects via identifiers embedded into them or their containers. In the context of a user's playback experience, a decoding process extracts the identifier from a media object and possibly additional context inform...	03/25/2008
7346824	Match circuit for performing pattern recognition in a performance counter A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask (�...	03/18/2008
7337346	Method and apparatus for fine tuning a memory interface A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the i...	02/26/2008
7321948	Highly available system test mechanism Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a firs...	01/22/2008
7320091	Error recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e...	01/15/2008
7315968	Phase error determination method and digital phase-locked loop system In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as ...	01/01/2008
7313753	Detector for detecting information carried by a signal having a sawtooth-like shape A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-...	12/25/2007
7313738	System and method for system-on-chip interconnect verification A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip componen...	12/25/2007
7307881	Non-volatile semiconductor memory with large erase blocks storing cycle counts In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such a...	12/11/2007
7292630	Limit-cycle-free FIR/IIR halfband digital filter with shared registers for high-speed sigma-delta A/D and D/A converters A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) share...	11/06/2007
7286614	Pilotless, wireless, telecommunications apparatus, systems and methods Systems, methods and apparatus are provided for demapping a received wireless signal. The wireless signal includes signal-bearing data without accompanying pilot signals, and demapping is accomplished by extracting information from the signal-bearing data by reducin...	10/23/2007
7281176	Determining signal quality and selecting a slice level via a forbidden zone In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier based on the number of data transitions at the first and second slice lev...	10/09/2007
7278071	Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the...	10/02/2007
7260755	Skewed inverter delay line for use in measuring critical paths in an integrated circuit An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a puls...	08/21/2007
7254345	Receiver and receiving method capable of detecting an eye aperture size formed by reception data signals In a receiver operable in response to a data signal, an eye aperture size is detected along a time axis by an eye aperture detection circuit and is controlled by a control circuit so that it becomes a maximum. The eye aperture detection circuit determines different ...	08/07/2007
7249293	Method and device for testing for the occurrence of bit errors In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial testing signal for is converted and demultiplexed into parallel signals corresponding to channels re...	07/24/2007
7230900	Optical disk apparatus and computer readable recording medium storing program An optical disk apparatus for forming an image on an optical disk according to dot data which defines density of dots of the image, the optical disk apparatus includes: a framing unit which makes a frame data by grouping a plurality of unit data, wherein when the do...	06/12/2007
7216267	Systems and methods for multistage signal detection in mimo transmissions and iterative detection of precoded OFDM Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the property that in a relatively simply decoding scheme such as mean squar...	05/08/2007
7199728	Communication system with low power, DC-balanced serial link A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set...	04/03/2007

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Class 714/709 - Data pulse evaluation/bit decision