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| Number | Title | Issue Date |
| 8037375 | Fast data eye retraining for a memory A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory.... | 10/11/2011 |
| 7814376 | Method and apparatus for frame delineation A frame delineation mechanism which alternately considers even and odd sync pattern position possibilities. With the addition of toggle logic, each of 66 possible states of even and odd alignment are exhausted in turn, odd, followed by even, followed by odd and so o... | 10/12/2010 |
| 7661039 | Self-synchronizing bit error analyzer and circuit A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler t... | 02/09/2010 |
| 7640463 | On-chip receiver eye finder circuit for high-speed serial link In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node ... | 12/29/2009 |
| 7631229 | Selective bit error detection at a bus device In one aspect, a data transmission rate of a message signal representing a bus message at a bus and a propagation delay between an occurrence of the message signal at a transmission output to the bus and an occurrence of the message signal at a receive input from th... | 12/08/2009 |
| 7506222 | System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master devi... | 03/17/2009 |
| 7472319 | Remote control signal receiver and remote control signal receiving method A remote control signal receiver receives a remote control signal in which bit signals are included as pulse signals. The remote control signal receiver includes a remote control signal receiving portion that receives a remote control signal, and a microcomputer. Th... | 12/30/2008 |
| 7444570 | Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit g... | 10/28/2008 |
| 7437643 | Automated BIST execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is p... | 10/14/2008 |
| 7434114 | Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training se... | 10/07/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7386767 | Programmable bit error rate monitor for serial interface A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag ge... | 06/10/2008 |
| 7386596 | High performance storage access environment The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can prov... | 06/10/2008 |
| 7373560 | Circuit for measuring signal delays of asynchronous inputs of synchronous elements A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during measurement operations. The delay between one of the test circuit's asy... | 05/13/2008 |
| 7356466 | Method and apparatus for performing observation probability calculations A method and apparatus for calculating an observation probability includes a first operation unit that subtracts a mean of a first plurality of parameters of an input voice signal from a second parameter of an input voice signal, and multiplies the subtraction resul... | 04/08/2008 |
| 7336735 | Viterbi decoder Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction is provided. The Viterbi decoder includes a branch metric calculation circuit for calculation of branch metrics for the received sequence of cod... | 02/26/2008 |
| 7328148 | Transferring compressed audio via a playback buffer A method for transferring real time information on a record carrier, typically bitstream audio on an optical disc, which method comprises encoding consecutive segments of the real time information to compressed real time data in frames, and determining a buffer occu... | 02/05/2008 |
| 7315660 | Refined quadrilinear interpolation A method of concealing error within a surface delimited by edges and containing points with which erroneous values are associated. A new value is interpolated for at least one point on the surface from interpolation points defined in a projection step by the project... | 01/01/2008 |
| 7308620 | Method to obtain the worst case transmit data and jitter pattern that minimizes the receiver's data eye for arbitrary channel model A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data sent by the transmitter is received by the receiver through the channe... | 12/11/2007 |
| 7290201 | Scheme for eliminating the effects of duty cycle asymmetry in clock-forwarded double data rate interface applications A clock management system receives an input clock signal having rising edges and falling edges, a first set of data values associated with the rising edges of the input clock signal, and a second set of data values associated with the falling edges of the input cloc... | 10/30/2007 |
| 7281175 | Readout controlling apparatus, reproducing apparatus, recording apparatus, and readout controlling method A readout controlling apparatus for controlling reading conditions at the time of reading data coded in units of predetermined code blocks from a recording medium capable of performing error correction at a high reliability even when the playback conditions are poor... | 10/09/2007 |
| 7278071 | Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the... | 10/02/2007 |
| 7275197 | Testing apparatus A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes an operation order holding unit for holding information indicating that a test operation by... | 09/25/2007 |
| 7260653 | Method and device for the synchronization between two networks The present invention relates to a method of synchronization between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter the synchronization is made ... | 08/21/2007 |
| 7251765 | Semiconductor integrated circuit and method for testing a semiconductor integrated circuit A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a ... | 07/31/2007 |
| 7249292 | Method for saving power in a user terminal after synchronization loss in broadband wireless access communication system Disclosed is a method for reducing power consumption of a user terminal when synchronization between a user terminal and a base station is disrupted in a broadband wireless access communication system. The method comprises the steps of: calculating first error rate ... | 07/24/2007 |
| 7246286 | Testing methods and chips for preventing asnchronous sampling errors Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second ope... | 07/17/2007 |
| 7246289 | Memory integrity self checking in VT/TU cross-connect A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a c... | 07/17/2007 |
| 7240266 | Clock control circuit for test that facilitates an at speed structural test When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can p... | 07/03/2007 |
| 7240238 | Remote data mirroring Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly acces... | 07/03/2007 |
| 7237167 | Testing apparatus A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes a first and a second testing modules, and a synchronization controlling unit. The synchroni... | 06/26/2007 |
| 7228466 | Method of detecting violation of block boundary and apparatus therefor A disk recording apparatus and method therefore including a boundary violation detector to determine whether a violation of a block boundary occurs on a disk by determining a phase difference between a block boundary signal and an encoding block synchronous signal. | 06/05/2007 |
| 7228465 | Bit rate agile onboard telemetry formatter A bit rate Agile Onboard Telemetry formatting system addresses the increased demands on the efficiency of telemetry systems. The present invention thins and reorders data streams, adjusting bit rates of a PCM stream using a bit-locked loop to match the desired infor... | 06/05/2007 |
| 7218861 | Optical transceiver, a multiplexing integrated circuit, a demultiplexing integrated circuit, an integral multiplexing/demultiplexing integrated circuit, and method for evaluating and testing the optical transceiver An optical transceiver 1 comprises first and second pseudo-random pattern generators 23 and 28 for generating a pseudo-random pattern signal, which are placed in a transmitting side path 6 and in a receiving side path 11 of the opt... | 05/15/2007 |
| 7216279 | Testing with high speed pulse generator An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at le... | 05/08/2007 |
| 7215360 | Error propagation tree technology A method and system for providing condition information associated with an entity being analyzed. The method includes presenting nodes corresponding to components of the entity according to a tree-like configuration, and providing condition information associated wi... | 05/08/2007 |
| 7210162 | DVB-ASI signal inverting adapter and system An inverting adapter is disclosed that inverts inverted DVB-ASI signals to produce an adapted DVB-ASI signal. This adapted DVB-ASI signal may be used by any DVB-ASI device. The inverting adapter can be contained in one small package and easily connected to any of th... | 04/24/2007 |
| 7203242 | Code rate adaptive encoding/decoding arrangement and method for a pulse code modulation system A code rate adaptive encoding/decoding arrangement and method for a pulse code modulation system comprises a code rate adaptor and a code capacity meter to dynamically produce a code rate adaptive signal for the code length of the pulse code modulation adaptive to a... | 04/10/2007 |
| 7197050 | Unit for transmitting data blocks in acknowledged mode on a channel featuring a radio link with a mobile station The transmitting unit comprises means for obtaining a sequence of data blocks to be transmitted on a channel, means for receiving information acknowledging the blocks of the sequence from an addressee unit, and means for controlling the transmission of the blocks of... | 03/27/2007 |
| 7171580 | Method and apparatus for enhancing system clock availability A method, apparatus, and computer instructions in a data processing system for managing clocks. The functionality of clock sources in the data processing system is verified to identify a set of valid clock sources in response to beginning an initial load process. Ha... | 01/30/2007 |
