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| Number | Title | Issue Date |
| 8176369 | Count data recording device, and method and program for recording count data The count data recording device includes: a storage unit including N memory areas; and a data restoring unit that detects a corruption in the count data pieces and restores the corruption, wherein the data writing unit records the count data piece using the memory a... | 05/08/2012 |
| 8078923 | Semiconductor memory device with error correction This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a sec... | 12/13/2011 |
| 7437643 | Automated BIST execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is p... | 10/14/2008 |
| 7430696 | Zeroing circuit for performance counter In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs... | 09/30/2008 |
| 7424651 | Method and apparatus for decision threshold control in an optical signal receiver An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and... | 09/09/2008 |
| 7424652 | Method and apparatus for detection of transmission unit loss and/or replication One embodiment of the disclosures made herein is a method of detecting a transmission unit fault condition in a network system. In accordance with such a method, an operation is performed for designating transmission units received at a first counting location of a ... | 09/09/2008 |
| 7404112 | Data selection circuit for performance counter In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receivin... | 07/22/2008 |
| 7395466 | Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag... | 07/01/2008 |
| 7392370 | Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each ... | 06/24/2008 |
| 7386767 | Programmable bit error rate monitor for serial interface A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag ge... | 06/10/2008 |
| 7369489 | Unbiased token bucket The present invention defines a method of unbiased policing of data flow in a network device. According to an embodiment of the present invention, the token bucket policer of the network device ‘permits’ (forwards) incoming packets even when the size of the toke... | 05/06/2008 |
| 7355965 | Apparatus and method for rapid detection of unidirectional breaks in a network ring Normal 802.3 Ethernet requires a tree topology. If a ring or a loop exists, then packets will be forwarded around the ring indefinitely. If the ring is broken, then there is no possibility of packets being propagated forever. This invention shows how to quickly impo... | 04/08/2008 |
| 7352886 | Error handling in a high throughput computer-aided detection environment A method and system for automated detection and handling of film feeding failures in a high-volume CAD environment. The method provides for batch processing a set of films including multiple film cases including the steps of providing a number count of the number of... | 04/01/2008 |
| 7349506 | Semiconductor integrated circuit and method for testing the same A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmissio... | 03/25/2008 |
| 7339887 | Multipoint protected switching ring Normal 802.3 Ethernet requires a tree topology. If a ring or a loop exists, then packets will be forwarded around the ring indefinitely. If the ring is broken, then there is no possibility of packets being propagated forever. This invention shows how to quickly impo... | 03/04/2008 |
| 7330695 | Bus powered wireless transmitter A process control system utilizes wireless transceivers to divorce the field devices from traditional wired network topologies. By providing field devices with wireless transceivers and shared wireless transceivers for adapting wired field devices, the field device ... | 02/12/2008 |
| 7331003 | Match circuit for performance counter In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit por... | 02/12/2008 |
| 7287183 | Electronic control unit First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value 3 is added to the adder-su... | 10/23/2007 |
| 7278078 | Built-in self-test arrangement for integrated circuit memory devices An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read f... | 10/02/2007 |
| 7228470 | Semiconductor testing circuit, semiconductor storage device, and semiconductor testing method A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counter... | 06/05/2007 |
| 7224703 | Method and apparatus for segmenting a data packet The efficiency of transmitting lower priority data traffic along with higher priority traffic is improved by segmenting a data packet in such a way so as to reduce transmission delay of the higher priority traffic. The data packet is segmented so that all its segmen... | 05/29/2007 |
| 7190667 | Link level packet flow control mechanism Some embodiments of the present invention include data network comprising a host system having a host-fabric adapter; at least one remote system; a switch fabric which interconnects said host system via said host-fabric adapter to said remote system along different ... | 03/13/2007 |
| 7124332 | Failure prediction with two threshold levels In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed. ... | 10/17/2006 |
| 7089440 | Skew compensation for a multi-agent shared bus A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to dete... | 08/08/2006 |
| 7032127 | Method and apparatus for identifying defective areas on a disk surface of a disk drive based on defect density A method and apparatus for detecting flaws requiring sparing of portions of storage media included as part of a hard disk drive are provided. A window of a selected portion of the storage medium is formed, and the density of defects detected within that window is ca... | 04/18/2006 |
| 7027395 | Method for marking packets of a data transmission flow and marker device performing this method A method for marking data packets of a data transmission flow pertaining to an end-to-end connection within a packet network is disclosed. The priority value is calculated based on at least one service quality parameter attributed to the data transmission flow, and ... | 04/11/2006 |
| 7024600 | Diagnosis of data transfer faults using constraints Method for diagnosing faults in a system under test (SUT) are provided. A representative method includes identifying at least some portions of the data transmission paths of the SUT capable of introducing errors in data transfer; providing constraints defining relat... | 04/04/2006 |
| 7006486 | Arrangement and a method in a switched telecommunication system The present invention relates to a telecommunication system giving the option to a user (A1) to select desired services. A switched domain (5) for transmission of data packets has switches (SW1), to which service providers (1–4), and ne... | 02/28/2006 |
| 6970436 | Apparatus for monitoring asynchronous transfer mode cells in communication systems An apparatus for monitoring asynchronous transfer mode cells in the communication system is proper for recognizing state information of asynchronous transfer mode cells transceiving between a base transceiver station and a base station controller. Accordingly, the a... | 11/29/2005 |
| 6965636 | System and method for block error correction in packet-based digital communications A system and method for efficiently correcting block errors in packet-based digital communications are provided whereby the ratio of redundant symbols/message symbols over the length of a data packet decreases in order to more efficiently use available bandwidth. Th... | 11/15/2005 |
| 6961879 | Apparatus and method for counting error rates in an optical compact disc storage system A method and system are disclosed for counting error rates occurring within an optical compact disk system as data is read from an optically encoded compact disk. In a preferred embodiment error flag data are generated as errors occur within the optical compact disk... | 11/01/2005 |
| 6959403 | Fault localization and health indication for a controller area network A node of a network comprises an error message detector arranged to detect error messages transmitted over the network, a counter arranged to count the error messages in order to produce an error message count, and a controller arranged to count valid messages in or... | 10/25/2005 |
| 6940808 | Adaptive rate traffic recovery mechanism for communication networks A traffic recovery mechanism for communication networks uses a layer-1 adaptive rate protection scheme that compliments layer-3 restoration mechanisms. The protection scheme allocates less bandwidth to the traffic during a protection switch than during... | 09/06/2005 |
| 6920591 | Measuring an error rate in a communication link An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to ... | 07/19/2005 |
| 6915463 | System and method for performing pre-emptive protection switching Methods and network nodes are provided which are adapted to perform protection switching on the basis of raw signal quality information, such as raw BER information, in a manner which instigates the protection switching before an actual failure has occurred. In some... | 07/05/2005 |
| 6907542 | System, device and method for determining the reliability of data carriers in a failsafe system network A network node, a system and method for facilitating safety in a communication network of a safety-related system, involving the means to accomplish the steps of receiving at a network note at least one packet, forming a relative measure of data corruption, and init... | 06/14/2005 |
| 6895536 | Testable up down counter for use in a logic analyzer A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predeter... | 05/17/2005 |
| 6891846 | Method and apparatus for a traffic shaper Packets of data from multiple queues are transferred onto a single channel. Each queue has associated with it a data rate for servicing a packet within the queue. Each queue has an integer that, relative to the other numbers, represents is inversely related to the a... | 05/10/2005 |
| 6862703 | Apparatus for testing memories with redundant storage elements A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and colum... | 03/01/2005 |
| 6810468 | Asynchronous FIFO circuit and method of reading and writing data through asynchronous FIFO circuit An asynchronous FIFO circuit has a memory; asynchronous read and write for reading a predetermined amount of data from and reading the predetermined amount of data into the memory on a first-in-first-out basis; | 10/26/2004 |
