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| Number | Title | Issue Date |
| 7743288 | Built-in at-speed bit error ratio tester A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (... | 06/22/2010 |
| 7739558 | Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associa... | 06/15/2010 |
| 7721162 | System for testing the upstream channel of a cable network A system for testing a portion of a cable network provides a pattern generator, Addresser, forward error corrector, and comparator. The system is particularly adapted to testing the upstream channel in a cable network. The pattern generator generates a test signal. ... | 05/18/2010 |
| 7702971 | System and method for predictive failure detection A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if ... | 04/20/2010 |
| 7689876 | Real-time optimized testing of semiconductor device A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the s... | 03/30/2010 |
| 7661038 | Link adaptation for retransmission error-control technique transmissions Embodiments of the present invention provide for link adaptation computations accounting for retransmission error-control techniques to be employed in transmission sequences utilizing the adapted link. Other embodiments may be described and claimed. ... | 02/09/2010 |
| 7631228 | Using bit errors from memory to alter memory command stream A system, method, and memory controller are provided that alters a memory command stream to a hardware memory. Data is written to the hardware memory and, after the data is stored in the memory, error correction code is received from the memory. Bit errors are ident... | 12/08/2009 |
| 7617424 | Error monitoring for serial links Methods, apparatuses and systems for physical link error data capture and analysis. ... | 11/10/2009 |
| 7613959 | Data receiving apparatus of a PCI express device A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circu... | 11/03/2009 |
| 7610520 | Digital data signal testing using arbitrary test signal For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is interpreted as an error in case the derived value does not substantially matc... | 10/27/2009 |
| 7607053 | Method and device for calculating bit error rate of received signal System and method of estimating radio channel bit error rate (BER) in a digital radio telecommunications system wherein the soft output of the turbo decoder is used as pointer or index to look-up-tables containing the bit-wise BER of a certain bit in the data field ... | 10/20/2009 |
| 7603591 | Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to gene... | 10/13/2009 |
| 7584389 | Turbo decoding apparatus and method This invention relates to a turbo decoding apparatus and method for a communication system. A high-rate memory buffer operating at the same frequency as a turbo decoder is arranged between a memory buffer of a receiver and the turbo decoder. The decoding apparatus r... | 09/01/2009 |
| 7571360 | System and method for providing a clock and data recovery circuit with a fast bit error rate self test capability A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a b... | 08/04/2009 |
| 7555685 | Method and apparatus for monitoring bit-error rate A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of differ... | 06/30/2009 |
| 7549094 | Method for receiving data by a universal asynchronous receiver transmitter The present invention discloses a method for receiving data by a universal asynchronous receiver transmitter, which includes a receive shift register (RSR), a receiver FIFO, a receiver buffer register (RBR), a line status register (LSR), and a good data length regis... | 06/16/2009 |
| 7523363 | Method and tester for determining the error rate of a mobile radio device with variable block allocation A method and tester for determining the error rate of a mobile radio device with variable block allocation is provided. Transmission blocks are sent to a mobile radio device to be tested. The mobile radio device to be tested receives and evaluates the transmission b... | 04/21/2009 |
| 7519874 | Method and apparatus for bit error rate analysis A method and apparatus for determining a bit error rate. The method comprises the steps of acquiring a data signal by an acquisition unit of a test instrument for a predetermined period of time, and storing the data signal in a memory of the test instrument. A clock... | 04/14/2009 |
| 7516373 | Method for testing the error ratio of a device using a preliminary probability A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BERlimit with an early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small pro... | 04/07/2009 |
| 7509541 | Detection mechanism A computer apparatus includes a first integrated circuit (IC) and a second IC. The second IC includes a soft error rate (SER) immune component and a SER component to detect radiation that could result in soft errors at logic at the first IC. ... | 03/24/2009 |
| 7509542 | System and method for testing the upstream channel of a cable network A system and method for testing a portion of a cable network provides a pattern generator, addresser, forward error corrector, and comparator. The system and method is particularly adapted to testing the upstream channel in a cable network. The pattern generator gen... | 03/24/2009 |
| 7496804 | Communications system, receiver, and method of estimating received signal quality by using bit error rate There is provided a receiver comprising a processing unit, a communications unit for receiving frames including training sequence symbols or pilot symbols, the processing unit being configured to use Cyclic Redundancy Check for detecting errors in the received frame... | 02/24/2009 |
| 7493530 | Method and apparatus for detecting an error in a bit sequence An error detector for a pseudo-random bit sequence (PRBS). A plurality of bits of a PRBS are received in a predictor circuit. A comparator compares two of the bits to predict a next bit in the sequence. The predicted next bit is compared with the actual next bit tha... | 02/17/2009 |
| 7484136 | Signal-to-noise ratio (SNR) determination in the time domain A technique for modifying communication operational parameters using fast, low complexity, accurately calculated SNR values. Techniques may improve upon prior art by calculating SNR values in a more time efficient and accurate manner in time domain. An agent may be ... | 01/27/2009 |
| 7475299 | Method and system for real-time bit error ratio determination A method and system for real-time bit error ratio determination is disclosed. According to one embodiment, a method is provided in which an operational link error rate of a link is determined and then used to estimate a real-time physical link error rate of the link... | 01/06/2009 |
| 7472318 | System and method for determining on-chip bit error rate (BER) in a communication system A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD ma... | 12/30/2008 |
| 7469366 | Measurement of health statistics for a high-speed interface Health of a high-speed interface link, such as a PCI Express link, is measured. In one embodiment, counter data representing data sent and errors occurring in a high-speed interface link is read. Health statistics based on the counter data are computed. The health s... | 12/23/2008 |
| 7467336 | Method and apparatus to measure and display data dependent eye diagrams A method and apparatus to draw eye diagrams of multi-valued signals that remove non-data dependent effects is disclosed. An exemplary method includes collecting event counts at variable bit offsets, desired time offsets within one or more bit periods and desired vol... | 12/16/2008 |
| 7467337 | Semiconductor memory device Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of... | 12/16/2008 |
| 7451362 | Method and system for onboard bit error rate (BER) estimation in a port bypass controller Certain aspects of the method may comprise receiving via a first port of the port bypass controller, a data stream comprising at least one known bit pattern. Upon locking onto at least a portion of the known bit pattern in the received data stream, a bit error rate ... | 11/11/2008 |
| 7444490 | Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device ... | 10/28/2008 |
| 7437643 | Automated BIST execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is p... | 10/14/2008 |
| 7434116 | Unitary testing apparatus for performing bit error rate measurements on optical components A testing apparatus for testing optical components includes an optical transmitter, an optical attenuator, an optical power meter and an optical receiver which are substantially rigidly coupled in a fixed relation to each other within a single housing. The system pe... | 10/07/2008 |
| 7434117 | Method and apparatus of determining bad frame indication for speech service in a wireless communication system A method of operating a receiver to determine a bad frame indication (BFI) of a received speech block includes decoding speech information bits of the received speech block; re-encoding the decoded speech information bits; comparing the received speech information b... | 10/07/2008 |
| 7434111 | Non-volatile memory system having a pseudo pass function A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs ... | 10/07/2008 |
| 7428669 | Adaptive FEC codeword management Adaptive FEC coding is used to adjust the codeword composition of FEC codewords in a communication system. A codeword composition ratio may be adjusted in response to variance of a measured transmission error value from a target transmission error value in the syste... | 09/23/2008 |
| 7426664 | Method for testing the error ratio of a device A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BERlimit with a early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small prob... | 09/16/2008 |
| 7424651 | Method and apparatus for decision threshold control in an optical signal receiver An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and... | 09/09/2008 |
| 7424077 | Jitter sensitive maximum-sequence detection A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected transition locations for transition shifts within a received signal and to in... | 09/09/2008 |
| 7423976 | Block error rate estimate reporting for target signal to interference ratio adjustment A method and apparatus is provided for reducing block error rate (BLER) estimate reporting to conserve system resources, while eliminating reports of BLER estimates unlikely to require an adjustment to target signal to interference ratio (SIR). A plurality of data b... | 09/09/2008 |
