Quotables
"There is no reason anyone would want a computer in their home."
Ken Olsen, chairman and founder of Digital Equipment Corporation ; 1977
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8166353 | Memory management apparatus A fault code memory management apparatus stores a permanent fault code in different places of a non-volatile memory, and restore the fault code when an error is detected in the fault code stored in the different places in a manner that, in case that discrepancy betw... | 04/24/2012 |
| 7994806 | System and method for testing embedded circuits with test islands Embodiments of the present disclosure relate to a system and method for testing an embedded circuit in a semiconductor arrangement as part of an overall circuit that is located on a semiconductor wafer, the system and method comprising an arrangement comprising an o... | 08/09/2011 |
| 7890817 | Protective system for an installation and a method for checking a protective system The invention relates to a protective system for an installation, in particular for a gas-turbine installation, in which all the fail-safe protective circuits with reaction time requirements of greater than 50 milliseconds are routed via a more fail-safe programmabl... | 02/15/2011 |
| 7797590 | Consensus testing of electronic system Consensus testing of electronic system. A tester (112) for testing an electronic system (100) includes: a traffic interface (114) to receive traffic (102) from a test of an electronic system (100); an element comparator (118... | 09/14/2010 |
| 7783938 | Result directed diagnostic method and system Provided is a method and system for diagnosing a test system to determine whether a condition of the test system contributed to an undesirable measurement result. The method includes interrogating a device under test comprising at least one of transmitting an electr... | 08/24/2010 |
| 7761751 | Test and diagnosis of semiconductors A method and system for performing diagnosing in an automatic test environment. The method begins by determining a fail condition during a test of a device under test (DUT). A diagnostic suite is determined for testing the fail condition. The diagnostic suite is gen... | 07/20/2010 |
| 7669090 | Apparatus and method for verifying custom IC An apparatus for verifying a custom IC including a test pattern generating unit for generating a test pattern for verifying a function of the custom IC. The test pattern is output to a master IC and a test IC. The apparatus further includes a comparing unit connecte... | 02/23/2010 |
| 7653842 | CRC format automatic detection and setting An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC fo... | 01/26/2010 |
| 7552367 | Fault recording and sequence of events recording device capable of recording communication-based signals related to electrical power systems A method for recording analog signals and digitally encoded information associated with primary and secondary devices of an electric power system includes: receiving a plurality of analog output signals and a plurality of ON/OFF status signals from the electric powe... | 06/23/2009 |
| 7519873 | Methods and apparatus for interfacing between test system and memory Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least ... | 04/14/2009 |
| 7437644 | Automatic self-testing of an internal device in a closed system A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from ... | 10/14/2008 |
| 7428674 | Monitoring the state vector of a test access port Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitor... | 09/23/2008 |
| 7412620 | Method for testing ability to recover from cache directory errors A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parit... | 08/12/2008 |
| 7409620 | Simplified high speed test system A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector... | 08/05/2008 |
| 7406628 | Simulated error injection system in target device for testing host system A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a fals... | 07/29/2008 |
| 7401269 | Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data co... | 07/15/2008 |
| 7395479 | Over-voltage test for automatic test equipment Automatic test equipment including a digital test instrument that may test for and respond to over-voltage conditions. Information on over-voltage conditions may be used in detecting or diagnosing fault conditions within a system under test. Over-voltage conditions ... | 07/01/2008 |
| 7395475 | Circuit and method for fuse disposing in a semiconductor memory device A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode i... | 07/01/2008 |
| 7392438 | Automatic safety test system An automatic safety test system, which comprises a control interface of a control unit for controlling the switching of a switch in a server unit and automatically switching to a specified testing point of an electronic product, and connects a bus interface of the c... | 06/24/2008 |
| 7373577 | CAN system Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error d... | 05/13/2008 |
| 7366957 | Method and apparatus for controlling SAS/fibre target behavior from a host The present invention is a method and system for providing a complete validation of an initiator and target within bus architecture. A target's behavior may be controlled by an initiator. Control of the target may be through execution of initiator commands including... | 04/29/2008 |
| 7366971 | Semiconductor memory having sub-party cell array error correction Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data accor... | 04/29/2008 |
| 7353438 | Transparent error correcting memory A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory ... | 04/01/2008 |
| 7350113 | Control method, system, and program product employing an embedded mechanism for testing a system's fault-handling capability A method of controlling a system is provided in which a control-data table is employed for facilitating operation of the system, and an inject-fault-data table is selectively used during testing of the system. Pursuant to the method, a security mechanism is provided... | 03/25/2008 |
| 7349506 | Semiconductor integrated circuit and method for testing the same A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmissio... | 03/25/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7340655 | Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with the Digital Visual Interface (DVI) standard. The skew adjustment circu... | 03/04/2008 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 02/26/2008 |
| 7331011 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second... | 02/12/2008 |
| 7325173 | Semiconductor memory having error correction During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the num... | 01/29/2008 |
| 7324982 | Method and apparatus for automated debug and optimization of in-circuit tests A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge fram... | 01/29/2008 |
| 7321996 | Digital data error insertion methods and apparatus Methods and apparatus are provided to insert errors into digital data. The errors can be inserted into the data itself, or into the corresponding error correcting code bits. The invention comprises a register, whose contents are combined with data using exclusive-OR... | 01/22/2008 |
| 7320096 | System and method for testing memory at full bandwidth There is disclosed systems and methods for testing a memory where at least one bit field at certain address locations cannot be directly accessed. In one embodiment, random bits are populated into a data field at one of the certain address locations, and at least so... | 01/15/2008 |
| 7318000 | Biometric quality control process Systems and methods configured to guide and manage laboratory analytical process control operations. A Biometric quality control (QC) process application is configured to monitor bias and imprecision for each test, characterize patient population data distributions ... | 01/08/2008 |
| 7302188 | Disperse equalizer and disperse equalizing method If no alarm is input from an optical receiver, an FEC decoder, or a client signal monitor, a control circuit controls a variable dispersion equalizer such that a transmission error becomes smaller using information on the number of error corrections obtained from th... | 11/27/2007 |
| 7302614 | Bus analyzer capable of managing device information A bus analyzer for tracing data flow on a bus which connects a host computer to peripheral devices, comprises an initialization information memory in which device information transferred by the peripheral device to the host computer at an initialization of connectin... | 11/27/2007 |
| 7296212 | Multi-dimensional irregular array codes and methods for forward error correction, and apparatuses and systems employing such codes and methods Methods, apparatuses, and systems for encoding information symbols comprising loading information symbols into a data array with n(1) rows and n(2) columns, wherein each column has ki(1) information symbols, and wherein k | 11/13/2007 |
| 7296207 | Communications protocol A method of communicating datagrams between terminals (nodes) of a communications system. In systems operating over unreliable media, redundancy check data can be included in a datagram for use in verifying the integrity of the datagram when received by a terminal; ... | 11/13/2007 |
| 7293206 | Test data pattern for testing a CRC algorithm A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a desired pattern of intermediate CRC values. The method includes generating... | 11/06/2007 |
| 7290197 | Correcting data using redundancy blocks Errors in data retrieved from a storage medium are corrected by retrieving a plurality of data blocks and a plurality of redundancy blocks associated with the plurality of data blocks from the storage medium. One or more data blocks retrieved from the storage medium... | 10/30/2007 |
