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| Number | Title | Issue Date |
| 7272681 | System having parallel data processors which generate redundant effector date to detect errors A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to ... | 09/18/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7272748 | Method and apparatus to detect and recover from a stack frame corruption A prologue and an epilogue of a function are hooked. Completion of the prologue is stalled in a first state of a stack frame, and a copy of the first state of the stack frame is saved. Completion of the prologue is initiated, permitting execution of the function. Co... | 09/18/2007 |
| 7272757 | Method for testing a memory chip and test arrangement A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correct... | 09/18/2007 |
| 7272674 | System and method for storage device active path coordination among hosts Systems, methods, apparatus and software can make use of persistent reservation commands to establish the port of a shared device that is to be used as an active port by one or more host computer systems coupled to the shared device. Information about one or more pa... | 09/18/2007 |
| 7269768 | Method and system to provide debugging of a computer system from firmware A method, system and article of manufacture to provide debugging of a computer system from firmware. A debugger in a first computer system is initialized during the pre-boot phase of the first computer system, the debugger to operate from a firmware environment of t... | 09/11/2007 |
| 7269765 | Method and apparatus for storing failing part locations in a module A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module, such as data query (“DQ”) terminals, identified during a testing procedure. After testing, the non-v... | 09/11/2007 |
| 7269528 | Method evaluating threshold level of a data cell in a memory device A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal a... | 09/11/2007 |
| 7269759 | Data processing apparatus and method for handling corrupted data values The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within t... | 09/11/2007 |
| 7266679 | System and method for reducing instability in an information handling system A system and method for reducing instability in an information handling system are disclosed. A method includes detecting a configuration change of a first memory device. Next, the method determines a device identifier for a second memory device depending on the con... | 09/04/2007 |
| 7266731 | Method and apparatus for managing remote software code update A method for managing remote software code update includes receiving a message from a remote device that includes a first code space having at least one segment and a second code space having one or more segment. The method also includes decoding the message to dete... | 09/04/2007 |
| 7266657 | Data protection device and method of securing data A data protection device capable of securing data in a data storage device is disclosed, comprising a disk space allotment unit, a marking unit, and an archiving unit. The disk space allotment unit undertakes to reorganize multiple sectors in the data storage device... | 09/04/2007 |
| 7266732 | MRAM with controller A memory card comprising an magnetic random access memory (MRAM) array that comprises a plurality of magnetic memory cells and a controller coupled to the MRAM array. The controller is configured to communicate with a host device, and the controller is configured pe... | 09/04/2007 |
| 7263627 | System and method having strapping with override functions A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be te... | 08/28/2007 |
| 7263577 | Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater numbe... | 08/28/2007 |
| 7263633 | Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for ... | 08/28/2007 |
| 7263027 | Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate... | 08/28/2007 |
| 7262479 | Layout structure of fuse bank of semiconductor memory device A fuse bank of a semiconductor memory device is provided. The fuse bank includes first and second laser fuses. The first laser fuse includes a first laser fusing region disposed in a first direction, a first connecting line region bent in a second direction, and a s... | 08/28/2007 |
| 7260495 | System and method for test generation for system level verification using parallel algorithms A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set colori... | 08/21/2007 |
| 7260759 | Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to... | 08/21/2007 |
| 7257654 | PCI bridge device configured for using JTAG scan for writing internal control registers and outputting debug state An integrated device (e.g., an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial... | 08/14/2007 |
| 7257684 | Method and apparatus for dynamically altering accessing of storage drives based on the technology limits of the drives A method and apparatus are disclosed for dynamically altering accessing of storage drives based on the technological limits of the drives. Operating parameters are set for each drive based on the technological limits for accessing that drive's type of technology. Th... | 08/14/2007 |
| 7257309 | Distributed storage of audio/video content Provided are systems and techniques for playing audio/video programs (e.g., movies) using a bank of networked audio/video players (e.g., digital projectors). Initially, a first portion (e.g., the majority) of an audio/video program is stored on a first audio/video p... | 08/14/2007 |
| 7257732 | Integrating content-laden media with storage system Integrating content into a storage system with substantially immediate access to that content. Providing high reliability and relatively easy operation with a storage system using redundant information for error correction. Having the storage system perform a “vir... | 08/14/2007 |
| 7256594 | Method and apparatus for testing semiconductor devices using the back side of a circuit board A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipme... | 08/14/2007 |
| 7254763 | Built-in self test for memory arrays using error correction coding A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment include... | 08/07/2007 |
| 7254748 | Error correcting content addressable memory A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entri... | 08/07/2007 |
| 7254813 | Method and apparatus for resource allocation in a raid system The present invention implements an I/O task architecture in which an I/O task requested by the storage manager, for example a stripe write, is decomposed into a number of lower-level asynchronous I/O tasks that can be scheduled independently. Resources needed by th... | 08/07/2007 |
| 7253606 | Framework that maximizes the usage of testhead resources in in-circuit test system A method and apparatus for maximizing the usage of a testhead of an in-circuit tester is presented. A testhead execution supervisor interfaces between a testhead controller and a graphical user interface used to enter manual tests. The testhead execution supervisor ... | 08/07/2007 |
| 7251714 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 07/31/2007 |
| 7251173 | Combination column redundancy system for a memory array A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant col... | 07/31/2007 |
| 7251753 | Apparatus, system, and method for identifying a faulty communication module An apparatus, method, and system associates an identifier with a data packet. The identifier uniquely identifies a communication module, such as a host interface card, within a data storage system. In operation, a computer host sends a data packet to a server. The c... | 07/31/2007 |
| 7249308 | Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls A system for testing logical partitioning. In a preferred embodiment, an I/O adapter is configured to break partitioning rules, for example, to attempt to access addresses outside a valid address range. Software is used to check for expected errors at expected addre... | 07/24/2007 |
| 7248592 | Partitionable data fabric and computing arrangement A circuit arrangement and method for interfacing a node and a data fabric. In a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, each node is assigned to one of a plurality of partitions. A node-interface circuit is configure... | 07/24/2007 |
| 7246268 | Method and apparatus for dynamic degradation detection Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors... | 07/17/2007 |
| 7246208 | Storage subsystem and storage subsystem control method The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions. A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be u... | 07/17/2007 |
| 7246300 | Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through ... | 07/17/2007 |
| 7246206 | Method and device for storing a computer program in a program memory of a control unit A method and a device for storing a computer program in a program memory of a control unit. The computer program is stored according to predefinable rules in specific memory areas of the program memory. To recognize an erroneous jump into an unused memory area of th... | 07/17/2007 |
| 7246262 | Storage subsystem and information processing system According to the invention, techniques for detecting and recovering from errors occurring in disk drive subsystems having a controller and drive units connected by a fibre channel loop. Specific embodiments can provide storage subsystems, methods and apparatus for u... | 07/17/2007 |
| 7246269 | Efficient memory check architecture and method Methods and apparatus are provided for use in testing a memory (230) coupled to a processing node (214). A background scrubber (316) in the processing node (214) is initialized to perform a test of the memory (230). A status of the... | 07/17/2007 |
