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| Number | Title | Issue Date |
| 5022007 | Test signal generator for semiconductor integrated circuit memory and testing method thereof A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored ther... | 06/04/1991 |
| 4882673 | Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache An integrated electronic circuit is provided comprising: a microprocessor for executing instructions; an instruction cache for storing instructions for execution by the microprocessor, the instruction cache being coupled to the microprocessor for transfer... | 11/21/1989 |
| 4833677 | Easily testable high speed architecture for large RAMS The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The addres... | 05/23/1989 |
| 4777586 | Semiconductor integrated circuit device with built-in arrangement for memory testing A semiconductor integrated circuit device which inhibits the output of programmed data of its built-in memory to external terminals but outputs the result of a comparison of the programmed data with an input signal supplied from a first external terminal ... | 10/11/1988 |
| 4744049 | Microcode testing of a cache in a data processor In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailab... | 05/10/1988 |
| 4661953 | Error tracking apparatus in a data processing system Disclosed is an error-tracking unit within a data processing system. Each data location to be checked for error and to be located in the case of an error is provided with error detection circuitry. Each data location is additionally provided with an error... | 04/28/1987 |
| 4641207 | Diagnostic device and method for examining the operation of a disk drive An external diagnostic device for examining the operation of a disk drive. The device is coupled to input terminals and output terminals of the drive and operates in a selected one of several modes at a given time. In a passive mode, the drive terminals a... | 02/03/1987 |
| 4622668 | Process and apparatus for testing a microprocessor and dynamic ram Process and apparatus for testing a microprocessor and dynamic RAM by a single tester where the microprocessor and dynamic RAM may be on a single card. The process makes the RAM appear static to an external static tester by separate read/write and refresh... | 11/11/1986 |
| 4575792 | Shared interface apparatus for testing the memory sections of a cache unit The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of... | 03/11/1986 |
| 4563736 | Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and co... | 01/07/1986 |
| 4479214 | System for updating error map of fault tolerant memory An online system is disclosed for mapping errors into an error map as data is transferred between a CPU and a relatively large fault tolerant semiconductor memory system without interfering with the normal use of the memory. The error mapping system permi... | 10/23/1984 |
| 4468731 | Identification apparatus for use in a controller to facilitate the diagnosis of faults A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers... | 08/28/1984 |
| 4342084 | Main storage validation means Method and means for validating any BSM in main storage while main storage remains available for normal system operation by all CPUs in the system. The system has plural sets of BSMs in which any set can be operationally fenced from system operation in or... | 07/27/1982 |
| 4317171 | LSI Microprocessor having an error processing circuit An LSI microprocessor comprising an instruction fetch portion and an instruction execute portion which fetches an instruction and executes an instruction independently of each other under a microprogram control, a pipeline control being made while synchro... | 02/23/1982 |
| 4227244 | Closed loop address An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory a... | 10/07/1980 |
| 4190885 | Out of store indicator for a cache store in test mode A Data Processing System comprises a central processor unit, a main memory and a cache, all coupled in common to a system bus. The central processor unit is also separately coupled to the cache. Apparatus in cache is responsive to signals received from th... | 02/26/1980 |
| 4103338 | Self-diagnostic method and apparatus for disk drive An exerciser is provided for use with a disk drive of the type having a microprocessor, a first memory for storing microcoded control programs for the drive, a second memory for storing instructions for the head carriage servo control apparatus, an addres... | 07/25/1978 |
| 4066880 | System for pretesting electronic memory locations and automatically identifying faulty memory sections An MOS RAM read/write memory system has thirty-two 1 × 512 bit RAM memory chips arranged in a matrix. The system pretests all data bit locations for each address prior to the entry of any data into that address, and automatically skips an address having ... | 01/03/1978 |
