Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7210084 | Integrated system logic and ABIST data compression for an SRAM directory ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid i... | 04/24/2007 |
| 7209860 | Distributed expert diagnostic service and system An expert diagnostic service system using a distributed architecture for generating expert diagnostic suggestions based on input received from a plurality of diagnostic systems. The expert service system collects data related to effective diagnostic results, such as... | 04/24/2007 |
| 7210059 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 04/24/2007 |
| 7206283 | High-performance network switch The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band c... | 04/17/2007 |
| 7203874 | Error detection, documentation, and correction in a flash memory device A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are era... | 04/10/2007 |
| 7203194 | Method and system for encoding wide striped cells A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into avail... | 04/10/2007 |
| 7203862 | Methods for controlling storage devices controlling apparatuses A storage device controller including: channel control portions each including a circuit board on which a file access processing portion for receiving file-by-file data input/output requests sent from information processors and an I/O processor for outputting I/O re... | 04/10/2007 |
| 7203890 | Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4... | 04/10/2007 |
| 7203905 | System and method for platform independent desktop lockdown A system and method that provides a platform-neutral shell application for a user interface is provided. The platform neutral shell application is performed in a way that prevents the user from accessing the underlying operating system. The desktop shell application... | 04/10/2007 |
| 7200706 | Semiconductor integrated circuit A semiconductor integrated circuit includes a local memory permitting high-speed access. The local memory has at least first and second ports. The first port of the local memory is connected to a CPU by a first bus and the second port of the local memory is connecte... | 04/03/2007 |
| 7200780 | Semiconductor memory including error correction function A semiconductor memory comprises, a data memory having a plurality of memory regions to store data at addresses specified, a code memory having the same address space as the data memory to store error correction codes, an error correction code control circuit includ... | 04/03/2007 |
| 7200056 | Memory row/column replacement in an integrated circuit An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual sol... | 04/03/2007 |
| 7197676 | Loop-Back Memory-Module Extender Card for Self-Testing Fully-Buffered Memory Modules A loop-back extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. An Advanced Memory Buffer (AMB) on the memory module fully buffers DRAM chips on t... | 03/27/2007 |
| 7196950 | Non-volatile semiconductor storage device performing ROM read operation upon power-on A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pad... | 03/27/2007 |
| 7197662 | Methods and systems for a storage system A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the man... | 03/27/2007 |
| 7197670 | Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) In accordance with various embodiments of the present invention, a cache-equipped semi-conductor device is provided with enhanced error detection logic to detect a first location-independent error within an area of the cache memory and prevent further use of the are... | 03/27/2007 |
| 7197632 | Storage system and cluster maintenance A method and system for maintaining a discovery record and a cluster bootstrap record is provided. The discovery record enables shared storage system discovery and the cluster bootstrap record enables cluster discovery and cooperative cluster startup. The cluster bo... | 03/27/2007 |
| 7197593 | Bad-sector search method, data recording device, and program While executing a command that accesses a sector on a disk-shaped recording medium placed in a data recording device, an address of a sector where it is difficult to read data is recorded in a memory. After that, a determination is made as to whether or not the data... | 03/27/2007 |
| 7194401 | Configuration for in-circuit emulation of a program-controlled unit A configuration contains a test unit that, during emulation, replaces a program-controlled unit that is used in normal operation of the system containing the program-controlled unit. The test unit has a first program-controlled unit and a second program-controlled u... | 03/20/2007 |
| 7194660 | Multi-processing in a BIOS environment A basic input/output system (BIOS) for use in a computer system having a plurality of processors is described. The BIOS is embodied in a computer readable medium as computer program instructions which are operable to facilitate substantially simultaneous operation o... | 03/20/2007 |
| 7194667 | System for storing device test information on a semiconductor device using on-device logic for determination of test results A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are sto... | 03/20/2007 |
| 7191357 | Hybrid quorum/primary-backup fault-tolerance model A hybrid quorum/consensus and primary-backup fault-tolerance model in an object-based distributed data storage system. When a primary manager fails, a hierarchy of network entities is established in which a group of realm managers first authorizes a failure-handling... | 03/13/2007 |
| 7191366 | Method and intelligent slave device transfer control unit for implementing seamless error resumption in a shared memory bus structure A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine whe... | 03/13/2007 |
| 7191367 | Storage unit, condition monitoring program product, and condition monitoring program storage medium The present invention provides a storage unit for accessing a storage medium according to a direction from a computer, a condition monitoring program product executed in the computer to which the storage unit is connected, and a storage medium thereof, having a conf... | 03/13/2007 |
| 7188272 | Method, system and article of manufacture for recovery from a failure in a cascading PPRC system A method of recovery from a data storage system failure in a data storage system having a host computer writing data to a first storage unit with a first storage controller synchronously mirroring the data to a second storage unit, and with a second storage controll... | 03/06/2007 |
| 7188199 | DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU accesses memory DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal and convert discrete samples thereof at a predetermined sampling rate... | 03/06/2007 |
| 7188225 | Storage system with disk drive power-on-reset detection A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an A... | 03/06/2007 |
| 7185222 | Apparatus, system, and method for maintaining data in a storage array An apparatus, system, and process are disclosed for maintaining data in an electronic storage array during multiple, concurrent drive failures. A first drive failure is recognized and the storage system controller subsequently enters a first operating mode. The stor... | 02/27/2007 |
| 7184916 | Apparatus and method for testing memory cards A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to b... | 02/27/2007 |
| 7185191 | Updatable firmware having boot and/or communication redundancy A distributed nodal system with a source computer processor node storing program code for target node(s). A target node has an updatable firmware memory storing program code for operating a target processor. The target code comprises application code for controlling... | 02/27/2007 |
| 7184352 | Memory system and method using ECC to achieve low power refresh Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndr... | 02/27/2007 |
| 7185246 | Monitoring of solid state memory devices in active memory system utilizing redundant devices Redundant capacity in a memory system is utilized to facilitate active monitoring of solid state memory devices in the memory system. All or part of the data stored in an active solid state memory device, and used in an active data processing system, may be copied t... | 02/27/2007 |
| 7181655 | Method and circuit arrangement for memory error processing The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an err... | 02/20/2007 |
| 7181643 | Method for comparing the address of a memory access with an already known address of a faulty memory cell A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided into banks and has an address structure in which each address is associated with a bank that is organize... | 02/20/2007 |
| 7181510 | Method and apparatus for creating a secure embedded I/O processor for a remote server management controller The present invention relates to providing a secure computing environment in a remote server management controller. The exemplary embodiment includes a hierarchy of register security levels restricting register access by communications interfaces shared by the remot... | 02/20/2007 |
| 7181672 | Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices A technique for coalesced Power Loss Recovery PLR status bits in an Error Correction Code ECC enabled flash memory. ... | 02/20/2007 |
| 7181659 | Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a fin... | 02/20/2007 |
| 7181641 | Data storage verification techniques for disk drivers Techniques are provided for verifying the integrity of data written onto a memory device under test. A pseudo random number generator generates data patterns based on a known ‘seed’ that includes a date and time. A data storage system writes the data patterns on... | 02/20/2007 |
| 7178018 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/13/2007 |
| 7178048 | System and method for signal synchronization based on plural clock signals A system includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency. The strobe signal is synchronized with the data signal based on a second clock ... | 02/13/2007 |
