Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 4759019 | Programmable fault injection tool A programmable fault injection tool (PFIT) for the texting of the diagnostic capabilities of a computer or digital processing system is disclosed. The PFIT is made up of event compare hardware and error injection hardware. The event compare hardware of th... | 07/19/1988 |
| 4747102 | Method of controlling a logical simulation at a high speed In a method of controlling a logical simulation of a logic circuit comprising a plurality of logic elements which can be simulated by forming a shift register string, the logical simulation is carried out without serial shift operation of the shift regist... | 05/24/1988 |
| 4744084 | Hardware modeling system and method for simulating portions of electrical circuits A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation ve... | 05/10/1988 |
| 4727545 | Method and apparatus for isolating faults in a digital logic circuit The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for... | 02/23/1988 |
| 4727313 | Fault simulation for differential cascode voltage switches A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals... | 02/23/1988 |
| 4726023 | Determination of testability of combined logic end memory by ignoring memory A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities... | 02/16/1988 |
| 4719626 | Diagnostic method and apparatus for channel control apparatus In a system where a central control unit, a main memory unit and a channel control unit are connected to a multi-bus, input/output control units are connected in series through the channel control unit and a common bus and each input/output unit, such as ... | 01/12/1988 |
| 4715035 | Method for the simulation of an error in a logic circuit and a circuit arrangement for implementation of the method A method for the simulation of an error in a logic circuit which comprises a bus optionally connectible to different logic levels, utilizes the assistance of input bit patterns from which output bit patterns are derived via a simulation model containing t... | 12/22/1987 |
| 4669083 | Apparatus for the simulation of the failure or satisfactory operation of a logic system An apparatus for simulating the failure or satisfactory operation of a system having a plurality of interconnected components. These components are subject to events, such as failures or repairs appearing in a sequentially combined manner. The apparatus c... | 05/26/1987 |
| 4654851 | Multiple data path simulator A multiple data path simulator for use with a data generator having a clock output and a data output including a data delay with a predetermined number of outputs, a data multiplexer for selecting one of the outputs, a clock delay with a predetermined num... | 03/31/1987 |
| 4631699 | Firmware simulation of diskette data via a video signal A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy... | 12/23/1986 |
| 4601032 | Test-generation system for digital circuits In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contain... | 07/15/1986 |
| 4544879 | Stimulus/measuring unit for DC characteristics measuring A novel digitized measuring system is disclosed for the measurement of the DC parameters of a wide variety of electrical and electronic devices. A stimulus measuring unit (SMU) is disclosed which can alternatively act as a voltage source and current monit... | 10/01/1985 |
| 4472804 | Method and means for reliability and maintainability analysis A failure simulation system utilizing fast failing units whereby system availability and reliability analysis can be completed in highly compressed periods of time. Each fast failing unit includes a random pulse generator and a variable failure rate pulse... | 09/18/1984 |
| 4456994 | Remote simulation by remote control from a computer desk A data processing system, comprising several distributed processing units which are connected to a remote central monitor and test station in which the state of each distributed processing unit is monitored by the transmission of test and diagnostic signa... | 06/26/1984 |
| 4397021 | Multi-processor automatic test system A test system utilizing a plurality of programmable test instruments each capable of executing portions of a test program with the test program being written in a compiler language such as ATLAS, for example, is disclosed. Programs specifying the tests to... | 08/02/1983 |
| 4380088 | Tester for collision-detect circuitry A tester for the collision detector of a transceiver for a multiple access data communications network using carrier-sense collision detection for controlling access to the network. A squelch circuit is employed in the transceiver's transmitter for enabli... | 04/12/1983 |
| 4308616 | Structure for physical fault simulation of digital logic A shift register connected to elementary gates is added to a digital network to form a fault simulator. The shift register and the additional gates can select a connection from the digital network and simulate a fault on the selected connection. Connectio... | 12/29/1981 |
| 4228537 | Method of and apparatus for automatic fault diagnosis of electrical circuits employing on-line simulation of faults in such circuits during diagnosis This disclosure is concerned with the use of on-line simulation of circuit faults during diagnosis to generate a small part of a complete fault dictionary needed for diagnosis of the circuit, being adapted for use of a mini-computer-based automated test s... | 10/14/1980 |
| 4156132 | Automatic fault injection apparatus and method An apparatus for simulating error conditions associated with an integrated circuit, the integrated circuit being an in-line component of an electronic circuit. The apparatus, in response to the receipt of specified commands, accepts and stores data and co... | 05/22/1979 |
