Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 8185782 | Test device and method for hierarchical test architecture A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controll... | 05/22/2012 |
| 8171341 | Method for controlling an operating mechanism and a manipulation unit A method for controlling an operating mechanism using a manipulation unit, in which the operating mechanism includes at least one microcontroller, at least one memory with a plurality of memory cells, and at least one debug interface, and the debug interface present... | 05/01/2012 |
| 8166343 | Processing system hardware diagnostics A method for diagnosing hardware failures in a data processing system includes a configuring a portion of a programmable logic device to create a state machine. The state machine tests a communication bus and a plurality of component devices connected by the communi... | 04/24/2012 |
| 8166344 | Method for controlling an operating mechanism and a manipulation unit A method for controlling an operating mechanism using a manipulation unit, in which the operating mechanism includes at least one microcontroller, at least one memory with a plurality of memory cells and at least one first value in a first memory cell and at least o... | 04/24/2012 |
| 8161327 | Process and system for the verification of correct functioning of an on-chip memory A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ... | 04/17/2012 |
| 8140902 | Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a co... | 03/20/2012 |
| 8140903 | Hardware process trace facility A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus... | 03/20/2012 |
| 8117498 | Mechanism for maintaining cache soft repairs across power state transitions A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repai... | 02/14/2012 |
| 8117497 | Method and apparatus for error upset detection and correction A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check s... | 02/14/2012 |
| 8112668 | Dynamic broadcast of configuration loads supporting multiple transfer formats A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers,... | 02/07/2012 |
| 8055946 | Semiconductor IC incorporating a co-debugging function and test system A semiconductor IC capable of debugging two or more processors at the same time using a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the process... | 11/08/2011 |
| 8055947 | Comparing supplied and sampled link ID bits on TMS lead An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different amo... | 11/08/2011 |
| 8041999 | Effecting adapter commands upon sequential target system TAP states A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at ... | 10/18/2011 |
| 8037355 | Powering up adapter and scan test logic TAP controllers A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second... | 10/11/2011 |
| 8024612 | Remote diagnosis system for medical appliances of modular design A method is disclosed for determining a configuration for a computer tomograph for the purpose of error diagnosis, a module, a computer tomograph and a system of appropriate design. The computer tomograph includes a multiplicity of detector modules. In at least one ... | 09/20/2011 |
| 8024613 | Method and system for managing apparatus performance The method comprises and executes constitutional information collection processing of collecting constitutional information of the apparatus, constitutional information of a logical unit which is a logical existence obtained by abstracting the apparatus, constitutio... | 09/20/2011 |
| 8015448 | System and method for conducting BIST operations A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to s... | 09/06/2011 |
| 8015447 | Processor debugging apparatus and processor debugging method A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the ... | 09/06/2011 |
| 7962793 | Self-diagnosing remote I/O enclosures with enhanced FRU callouts A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. When a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using t... | 06/14/2011 |
| 7962794 | Computer chip set having on board wireless interfaces to support test operations A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a proc... | 06/14/2011 |
| 7958472 | Increasing scan compression by using X-chains To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unloa... | 06/07/2011 |
| 7941702 | Electronic control unit An ECU that controls an engine of a vehicle includes a MPU and an IC that monitors the operation of the MPU. The MPU is programmed to execute a verification result check and test selection function for selecting a test for verifying the function of the MPU. The MPU ... | 05/10/2011 |
| 7930592 | Enabling memory redundancy during testing A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array. ... | 04/19/2011 |
| 7913120 | Selective disabling of diagnostic functions within a data processing system A data processing system 2 has a memory 6 with a memory address space incorporating a plurality of domains, each domain comprising a set of memory addresses as defined by programmable domain specifying data 32. A processor core 8 executes... | 03/22/2011 |
| 7908520 | Self-testing and -repairing fault-tolerance infrastructure for computer systems ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these... | 03/15/2011 |
| 7900090 | Systems and methods for memory retention across resets Systems and methods (“utility”) for providing a computer system with a mechanism to record live data on a continuous basis which may be analyzed subsequent to a fault condition is provided. The utility uses the existing DRAM memory of a computer system as a rete... | 03/01/2011 |
| 7890804 | Program memory test access collar A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor me... | 02/15/2011 |
| 7870429 | Control apparatus For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor cores (2a, 2b) connected to a boundary... | 01/11/2011 |
| 7870428 | Method of diagnosing circuit board, circuit board, and CPU unit In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of... | 01/11/2011 |
| 7865773 | System, method, and device including built-in self tests for communication bus device A method, device, and system including built-in self tests for a communication bus device is disclosed. In one form, a method of testing a device operable to be coupled to a communication port an information handling system includes accessing a configuration descrip... | 01/04/2011 |
| 7844857 | Writing data processing control apparatus, writing method, and writing apparatus A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing appa... | 11/30/2010 |
| 7836342 | Providing maintenance access via an external connector This invention relates to a method, an apparatus, an electronic device, a system, and a computer program product for selecting at least one component out of at least one maintenance component and at least one non-maintenance component, wherein said at least one main... | 11/16/2010 |
| 7831862 | Selective timer control during single-step instruction execution A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the i... | 11/09/2010 |
| 7823017 | Structure for task based debugger (transaction-event-job-trigger) Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to a... | 10/26/2010 |
| 7809987 | Accepting link ID upon supplied and sampled bits matching An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different amo... | 10/05/2010 |
| 7802141 | Semiconductor device having one-chip microcomputer and over-voltage application testing method A booster circuit is incorporated in a one-chip microcomputer. In a test mode, a burn-in test is performed by switching power supply systems so that a power supply voltage of 5V is supplied to a 3.3V-type circuit section that normally operates on a power supply volt... | 09/21/2010 |
| 7802142 | High speed serial trace protocol for device debug Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of... | 09/21/2010 |
| 7793152 | Zero-bit scans defining command window and control level A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at ... | 09/07/2010 |
| 7783925 | Receiving control, data, and control segments of communication scan packets A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system ... | 08/24/2010 |
| 7779301 | Computer chip set having on board wireless interfaces to support test operations A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a proc... | 08/17/2010 |
