Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 6047384 | Rapid recovery and start-up system for peripheral systems The start-up of a computer system takes place rapidly using a computer system having a recovery system which collects data for the recovery in parallel fashion in a common memory so that the data can be transferred to peripheral units of the computer syst... | 04/04/2000 |
| 6047294 | Logical restore from a physical backup in a computer storage system Method and apparatus for backing up and restoring data in a computer system is disclosed. A segment of data, such as a virtual disk partition, may be backed up at a physical level from a primary storage device to a backup storage device. A logical element... | 04/04/2000 |
| 6038678 | Path switching method, path switching apparatus and nodes of UPSR An alarm detect unit (a path switching apparatus) for selecting an active path comprises a path-alarm detect circuit and a guard timer for a working path as well as a path-alarm detect circuit and a guard timer for a protection path. When an alarm is dete... | 03/14/2000 |
| 6035326 | Mapping table lookup optimization system The present invention is a system and method for creating lookup trees of mapping specifications for multiprotocol messaging environments. Source data, which is preferably updated infrequently, is compiled into a hierarchical tree, which is stored in a fi... | 03/07/2000 |
| 6035416 | Method and apparatus for interface dual modular redundancy Controller triple modular redundancy is substantially achieved and reliability improved in a system having duplicate controllers that serve peripheral units. Both controllers detect suspected faults in itself and in the other controller. A peripheral unit... | 03/07/2000 |
| 6021511 | Processor This invention discloses a processor with a plurality of execution units integrated into a chip. The execution unit has an initial failure signal output device which provides an initial failure signal when there is an initial failure in its own execution ... | 02/01/2000 |
| 6012149 | Computer system with polymorphic fault processing A computer system includes a main processor and a supervisory processor. The main processor provides status signals when a fault condition exists and responds to control signals for fault recovery. The supervisory processor instantiates objects from a fau... | 01/04/2000 |
| 6012114 | System for preventing software of a computer system from interacting with a connector to avoid data corruption due to surprise removal of a circuit card A computer system has a connector and a circuit card that is inserted in the connector. A mechanism that is associated with the connector and the card has a state for indicating when the card is secured to the connector. A controller of the computer syste... | 01/04/2000 |
| 6006341 | Bus arrangement related to a magazine The invention relates to a magazine-related bus arrangement, wherein the magazine includes a backplane (1a) having electric contact fields and means for holding a number of circuit boards having edge-related electric contact surfaces in electric coaction ... | 12/21/1999 |
| 6006352 | Bitstream decoding apparatus with reduced error correction processing and decoding method A decoding apparatus and a decoding method are capable of minimizing degradation of the quality of images and sounds when a synchronous signal error occurs. The decoding apparatus includes a frame counter for receiving a bit stream, a synchronous pattern ... | 12/21/1999 |
| 5996086 | Context-based failover architecture for redundant servers In a redundant server network system, failover services for a failed server are provided by a survivor server belonging to a common failover group. At startup of a local server process running on the survivor server, a context is created for the local ser... | 11/30/1999 |
| 5991900 | Bus controller A bus controller for a computer system. The controller comprises a monitor for monitoring request signals and response signals between a first component and a second component each connected to a bus of the computer system; and a terminator controlled by ... | 11/23/1999 |
| 5991517 | Flash EEprom system with cell by cell programming verification A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased tog... | 11/23/1999 |
| 5964886 | Highly available cluster virtual disk system A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reli... | 10/12/1999 |
| 5933592 | Promoting device level error to raidset level error to restore redundacy in a raid array data storage system A RAID array includes redundant storage devices. Data is distributed across the storage devices, and organized as slivers of RAID protected data blocks. This redundancy provides for the reconstruction of valid data when data at a particular data block of ... | 08/03/1999 |
| 5933422 | Communication network recoverable from link failure using prioritized recovery classes In a self-healing network, virtual paths between user terminals are classified according to different fault recovery priority levels and communication links are mapped to virtual paths accommodated by the links and to bandwidths remaining in the respectiv... | 08/03/1999 |
| 5926620 | Content addressable bit replacement memory A method of storing data to a defective memory device includes first receiving a memory address and a plurality of data bits. Next, a content addressable memory is interrogated with the memory address. Then, at least one data bit of the plurality of data ... | 07/20/1999 |
| 5901279 | Connection of spares between multiple programmable devices A method of coupling logic devices using spares. A first logic device is coupled to a second logic device using a first plurality of spares. The first logic device is coupled to a third logic device using a second plurality of spares. The second logic dev... | 05/04/1999 |
| 5896492 | Maintaining data coherency between a primary memory controller and a backup memory controller A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with a tap coupled to the i... | 04/20/1999 |
| 5892893 | Device for the bus-networked operation of an electronic unit with microcontroller, and its use A device for bus-networked operation of an electronic unit having microcontroller has a semiconductor circuit which is supplied from a superordinate potential, and is connected between a bus protocol module of the microcontroller and the cores of a two co... | 04/06/1999 |
| 5892890 | Computer system with parallel processor for pixel arithmetic A pixel processor, for use in conjunction with a color video monitor or an all points addressable color print engine, includes brush logic, mask logic, clip logic, and a multi-pixel logic unit to produce a page map consisting of millions of pixels, each h... | 04/06/1999 |
| 5872904 | Computer system using a master processor to automatically reconfigure faulty switch node that is detected and reported by diagnostic processor without causing communications interruption A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network ... | 02/16/1999 |
| 5867382 | Generic control systems using a virtual rack module A Virtual Rack module for a programmable logic controller. The Virtual Rack module comprises a subroutine written using a programming language understandable to the programmable logic controller, preferably using the relay ladder logic programming languag... | 02/02/1999 |
| 5864654 | Systems and methods for fault tolerant information processing A fault-tolerant management information system includes three or more data management systems (e.g. data base systems) that replicate data. Data access requests resulting from user requests to application systems are issued by user request processing enti... | 01/26/1999 |
| 5862396 | Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system In a main memory with arithmetic logic processing capability, k first memories (k is an integer equal to or more than 0) are connected to a memory bus, for storing data. M second memories with arithmetic logic processing capability (m is an integer equal ... | 01/19/1999 |
| 5852722 | System and method for automatic configuration of home network computers A distributed computer network comprising of unconfigured network home client computers, and at least one autoconfiguration server. The network may also include sales servers and local service provider servers. The home network client computer determines ... | 12/22/1998 |
| 5826000 | System and method for automatic configuration of home network computers An automated configuration system and method configures home network client computers, including determining local service provider information, without any user assistance. The distributed computer network includes network home client computers and at le... | 10/20/1998 |
| 5815647 | Error recovery by isolation of peripheral components in a data processing system The present invention provides a computer system which allows a user to identify which one of a plurality of feature cards has issued an error signal. The device issuing the error signal is then isolated and error recovery techniques, (or re-initializatio... | 09/29/1998 |
| 5790771 | Apparatus and method for configuring a reconfigurable electronic system having defective resources An arrangement for configuring a reconfigurable system having a plurality of resources includes a compiler that configures the resources to implement a functional system in accordance with a user design. A defect database is also provided that (1) stores ... | 08/04/1998 |
| 5784702 | System and method for dynamically performing resource reconfiguration in a logically partitioned data processing system A dynamic reconfiguration request for a change in a system's physical configuration is transmitted from a configuration controller to a hypervisor controlling operating systems executing in one or more partitions of the system. The hypervisor translates t... | 07/21/1998 |
| 5768493 | Algorithm for fault tolerant routing in benes networks Benes networks are used in SIMD single instruction multiple data parallel processing systems to provide interprocessor communication. The invention describes an algorithm which will allow these networks to be used in presence of several faults, without re... | 06/16/1998 |
| 5764920 | System and method for routing administrative data over a telecommunications network to a remote processor A system and method for routing administrative data over a telecommunications network to a remote processor establishes a connection between a router and the remote processor over a primary link. A processor associated with the router is adapted to detect... | 06/09/1998 |
| 5765211 | Segmenting non-volatile memory into logical pages sized to fit groups of commonly erasable data An electronic component including an electrically erasable non-volatile memory for storing information structured in logical entities that are managed by a memory manager. The memory is segmented into pages for the purpose of erasing the information. The ... | 06/09/1998 |
| 5761428 | Method and aparatus for providing agent capability independent from a network node An improved network node includes a network node autonomy portion and a sentinel autonomy portion. The network node autonomy portion can perform the tasks as a conventional network node. Both the autonomy portions contain their respective processors and M... | 06/02/1998 |
| 5751574 | Method for loading software in communication systems with non-redundant, decentralized equipment In a method for loading software in communication systems with non-redundant, decentralized equipment so that the availability of a communication system for the connected subscribers remains assured during the loading process of programs and data, there i... | 05/12/1998 |
| 5745669 | System and method for recovering PC configurations A computer utility automatically monitors changes in configuration files stored on the computer hard disk. The recovery tool indicates to the user when changes are detected in the configuration files and provides the option to restore the configuration fi... | 04/28/1998 |
| 5739761 | Vehicular controller A vehicle is equipped with an engine control ECU, an anti-lock brake system control ECU, a transmission control ECU and a meter control ECU. Each ECU shares information with the others by communicating and by performing mutual malfunction diagnosis operat... | 04/14/1998 |
| 5727143 | Fault-tolerant system capable of rapidly recovering a system function when a functional block becomes a faulty block A fault-tolerant system has a predetermined system function and comprises a plurality of functional blocks. The fault-tolerant system uses selected ones of the functional blocks to construct the predetermined system function and uses a remaining one of th... | 03/10/1998 |
| 5712967 | Method and system for graceful recovery from a fault in peripheral devices using a variety of bus structures A method and system for resetting a peripheral device which could use a variety of buses have been disclosed. The method and system determine what bus type the peripheral device has. The method and system then automatically execute a reset process capable... | 01/27/1998 |
| 5708789 | Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate... | 01/13/1998 |
