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| Number | Title | Issue Date |
| 8108729 | Memory-based trigger generation scheme in an emulation environment A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from... | 01/31/2012 |
| 8108728 | Method and apparatus for operational-level functional and degradation fault analysis An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from ... | 01/31/2012 |
| 7913119 | Method and device for verifying integrity of data acquisition pathways Disclosed is a method of verifying the integrity of data acquired from a device emulating a hard disk to a host computer over a data transfer pathway. A storage medium containing known data is connected to the data transfer pathway, the storage medium capable of emu... | 03/22/2011 |
| 7685467 | Data system simulated event and matrix debug of pipelined processor A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a... | 03/23/2010 |
| 7676697 | Using a delay line to cancel clock insertion delays A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted dynamically at runtime to optimize the performance of the interface. ... | 03/09/2010 |
| 7613951 | Scaled time trace The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may ... | 11/03/2009 |
| 7493519 | RRAM memory error emulation A method for verifying the functionality of a repair system of configurable memory that functions to replace memory that fails predetermined tests with unused memory that passes the tests. The method includes the steps of providing a matrix comprising a plurality of... | 02/17/2009 |
| 7415700 | Runtime quality verification of execution units One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of ... | 08/19/2008 |
| 7389218 | Hardware and software co-simulation method for non-blocking cache access mechanism verification A hardware and software co-simulation method for non-blocking cache access mechanism verification is provided. The method is applied for cache access mechanism verification. First, at least one way buffer is added into the software modeling, then the hardware and so... | 06/17/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
| 7343591 | Real-time data exchange on demand A real time data exchange on demand system for transferring real time data between a host processor and a target processor is described. The target processor includes a real time target exchange library and API library interface to a target application. The host pro... | 03/11/2008 |
| 7337368 | System and method for shutdown memory testing In accordance with the teachings of the present disclosure, a system and method for reducing the amount of time for a boot operation is provided that substantially reduces disadvantages and problems associated with previously developed memory testing systems and met... | 02/26/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7319340 | Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated... | 01/15/2008 |
| 7318017 | Collecting and exporting on-chip data processor trace and timing information with differing collection and export formats Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. ... | 01/08/2008 |
| 7318174 | Systems, methods, and computer readable medium for analyzing memory Techniques are provided for expanding the functionality of live memory analysis commands to analyze a memory dump or other differing memory types. To this end, a live memory command which normally analyzes live memory is modified to invoke a virtual machine. Live me... | 01/08/2008 |
| 7313729 | Low-cost debugging system with a ROM or RAM emulator A low-cost micro-controller debugging system with a ROM or RAM emulator is disclosed. The system includes a target microcontroller (MCU) and at least one ROM connected together, with a debugger unit which debugs that target MCU. A ROM/RAM emulator is connected to th... | 12/25/2007 |
| 7284169 | System and method for testing write strobe timing margins in memory devices Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a tra... | 10/16/2007 |
| 7284155 | Remote software support agent system with electronic documents for troubleshooting A method of and system for troubleshooting a first computer system using a second computer system having a processor and a memory storing an electronic document including troubleshooting information and storing a set of troubleshooting commands for execution by the ... | 10/16/2007 |
| 7281076 | Form factor converter and tester in an open architecture modular computing system A converter assembly comprises a backplane interface to a backplane compliant with a first open architecture modular computing system standard, a component interface capable of coupling to a component compliant with a second open architecture modular computing syste... | 10/09/2007 |
| 7278123 | System-level test architecture for delivery of compressed tests An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data ... | 10/02/2007 |
| 7269724 | Remote field upgrading of programmable logic device configuration data via adapter connected to target memory socket A method and apparatus are provided for updating or changing configuration data stored in the PROM of a target system, the data being used to configure one or more reprogrammable logic devices such as FPGAs. In one embodiment the apparatus comprises a modem used to ... | 09/11/2007 |
| 7249288 | Method and apparatus for non-intrusive tracing A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information t... | 07/24/2007 |
| 7222051 | Working machine, failure diagnosis system for work machine and maintenance system for work machines A working machine maintenance system having a plurality of working machines. A center server is provided that manages maintenance on the plurality of working machines by engaging in data exchange through bidirectional communication with each of the plurality of work... | 05/22/2007 |
| 7222315 | Hardware-based HDL code coverage and design analysis Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with... | 05/22/2007 |
| 7210064 | Program controlled unit and method for debugging programs executed by a program controlled unit The described program controlled unit has first supply voltage connections for applying a first supply voltage to the program controlled unit and second supply voltage connections for applying a second supply voltage to the program controlled unit. The full OCDS mod... | 04/24/2007 |
| 7177986 | Direct access mode for a cache A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons a... | 02/13/2007 |
| 7171593 | Displaying abnormal and error conditions in system state analysis An embodiment of the present invention is a technique for providing a graphical user interface (GUI) to view system state of a computer system. An error window displays an error condition of a failed unit in a plurality of functional units in a computer system based... | 01/30/2007 |
| 7165198 | System for testing an integrated circuit using multiple test modes A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage device... | 01/16/2007 |
| 7162663 | Test system and method for testing memory circuits A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a func... | 01/09/2007 |
| 7155370 | Reusable, built-in self-test methodology for computer systems A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer ... | 12/26/2006 |
| 7145818 | Semiconductor integrated circuit device having test circuit A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a memory or at the input of a logic stage, a signal selector is provided in... | 12/05/2006 |
| 7130787 | Functional replicator of a specific integrated circuit and its use as an emulation device A real time functional replicator (10) of a specific integrated circuit comprised of a processing unit and peripherals in order to perform specific digital and/or analog functions controlled by specific software, this specific integrated circuit being designe... | 10/31/2006 |
| 7124324 | Method of testing fiber channel ports in a storage server at full bandwidth without connection to external devices A data storage system includes a plurality of disk drives for data storage. A storage server controls the reading and writing of data to the disk drives. The storage server can be tested prior to connecting the disk drives and other components of the data storage sy... | 10/17/2006 |
| 7103530 | System for integrating event-related information and trace information An emulation and debugging system that includes an in-circuit emulator couplable to a microcontroller. The in-circuit emulator is adapted to execute an event thread in lock-step with the microcontroller. Event information generated as a result of executing the event... | 09/05/2006 |
| 7096142 | Report format editor for circuit test A graphical user interface (GUI) of a report format editor for circuit test displays a number of user-selectable representations of circuit test data. The GUI also displays a user-modifiable ASCII report format that is formed, at least in part, of placed ones of the... | 08/22/2006 |
| 7096322 | Instruction processor write buffer emulation using embedded emulation control instructions Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in... | 08/22/2006 |
| 7079982 | Working machine, trouble diagnosis system of working machine, and maintenance system of working machine A working machine failure diagnosis method for performing a failure diagnosis by transmitting and receiving signals through communication devices provided at a working machine and at an information management center, according to the present invention, includes: a f... | 07/18/2006 |
| 7076419 | Using sign extension to compress on-chip data processor trace and timing information for export An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality ... | 07/11/2006 |
