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| Number | Title | Issue Date |
| 6058447 | Handshake circuit and operating method for self-resetting circuits In a circuit that generates a plurality of dynamic signals in a self-resetting signal path, none of which may occur in some cycles, a handshake circuit generates a signal indicative of whether none of the signals occurred and incorporates the plurality of... | 05/02/2000 |
| 6049893 | System and method for synchronously resetting a plurality of microprocessors A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and t... | 04/11/2000 |
| 6038684 | System and method for diagnosing errors in a multiprocessor system A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and t... | 03/14/2000 |
| 6026499 | Scheme for restarting processes at distributed checkpoints in client-server computer system A scheme for restarting processes at distributed checkpoints in a client-server computer system, in which a fault in one client computer does not affect the server computer and the other client computers. In this scheme, a fault occurring in one computer ... | 02/15/2000 |
| 6003140 | Method and device for monitoring an electronic computing unit The invention concerns a method and an arrangement for monitoring a computing unit, such as is used, for example, in control devices. The monitoring device generates a reset signal if the supply voltage drops below a voltage level, below which a defined o... | 12/14/1999 |
| 5991896 | Method and apparatus for protecting an electronic system from erroneous operation due to static electricity A technique for protecting an electronic system having a programmable input/output interface from erroneous operation due to static electricity includes the steps of: (a) setting an internal timer for continuously resetting a program state of the input/ou... | 11/23/1999 |
| 5983362 | Non-interrupted operation control apparatus for a modulator-demodulator A non-interrupted operation control apparatus for a modem is provided for the purpose of preventing communications errors caused by the corruption of control parameter data stored within the modem, and circuit hangs, wherein an initialization unit is prov... | 11/09/1999 |
| 5966305 | Control system having effective error detection capabilities A control system has a plurality of processors connected in a series order. Each of the processors monitors a preceding processor for operating abnormalities. If an abnormality is detected the operation of abnormal preceding processor is terminated and a ... | 10/12/1999 |
| 5964888 | Circuit arrangement for executing a reset A circuit arrangement for executing a reset, in which controlled resetting of a functional computer and a safety module takes place. A reset stage is able to coerce both the functional computer and the safety module into a reset state, while all output st... | 10/12/1999 |
| 5956475 | Computer failure recovery and alert system A computer system includes a timer which times out if the operating system does not periodically reset the timer. When the system fails and no longer resets the timer, the timer times out, and the computer is reset. The system performs its power on progra... | 09/21/1999 |
| 5884022 | Method and apparatus for controlling server activation in a multi-threaded environment A method and apparatus for controlling server activation. In the prior art, there exists a race condition between the shutting down of an old server and the starting up of a new server. Further, rapidly restarting servers, such as daemonic servers, are pr... | 03/16/1999 |
| 5864656 | System for automatic fault detection and recovery in a computer system A system for automatic fault detection and recovery in a computer system includes: a system fault detector, a halt time duration counter, and program and hardware recovery signal generators. The system fault detector is connected to a plurality of bus sig... | 01/26/1999 |
| 5864663 | Selectively enabled watchdog timer circuit A watchdog timer circuit includes a cyclic counter having an overflow signal that functions as a reset pulse to a microprocessor. The timer circuit includes a feature for selectively supplanting the overflow signal to enable in situ programming of the mic... | 01/26/1999 |
| 5838896 | Central processing unit for preventing program malfunction An improved CPU for preventing a program malfunction which is capable of preventing a malfunction of a program by resetting the CPU when an abnormal data is fetched from a memory due to a noise, which includes a program counter for designating an address ... | 11/17/1998 |
| 5828822 | Watchdog circuit for carbon monoxide monitors A microcontroller supervision circuit comprising an electronic control capable of causing a high-impedance on at least one external pin upon occurrence of a reset condition. A supervision circuit is coupled to the at least one external pin for detecting t... | 10/27/1998 |
| 5826205 | Reprogrammable controller containing multiple programs A controller has a microcomputer, an electrically erasable and programmable memory which has a control program (CONTROL), a read only memory and a serial interface. A serial data transmission line can be connected to the serial interface. A program (PROG)... | 10/20/1998 |
| 5805791 | Method and system for detection of and graceful recovery from a peripheral device fault A system and method for detecting and gracefully recovering from a peripheral device fault has been disclosed. The method detects whether a peripheral device has suffered from a peripheral device fault. Where the peripheral device fault has occurred, the ... | 09/08/1998 |
| 5805790 | Fault recovery method and apparatus In a fault recovery method for a multi-processor system including a main storage and a plurality of virtual machines which are assigned to a plurality of processors under control of a host operating system and a plurality of guest operating systems and wh... | 09/08/1998 |
| 5802485 | Control device including an electrically programmable memory A control device has a microcomputer, a memory which has a control program and can be cleared and programmed electrically, a read-only memory and a serial interface. In the read-only memory, a program for reprogramming the memory which can be cleared and ... | 09/01/1998 |
| 5790419 | Fail-safe system and method of operation A system is provided to automatically terminate a fail-safe state. When an abnormality detection signal of Lo and a pulse having a frequency outside a specified range are input to set and reset terminals S, R of an R-S Flip-Flop (R-SFF) 24, respectively, ... | 08/04/1998 |
| 5784625 | Method and apparatus for effecting a soft reset in a processor device without requiring a dedicated external pin A system and method for emulating the state of a soft reset within a processor device without requiring a dedicated soft reset external pin associated with said processor device. The novel system includes control circuitry coupled to a processor device fo... | 07/21/1998 |
| 5774642 | Architecture for dynamic service processor exchange providing multitasking environment where multiple processors have access to a system configuration table A computer system for dynamic service processor exchange comprising a first, active service processor connected by a network and a maintenance unit (CMU) to a central system (4) and to a second, backup service processor (2). Each service processor has, in... | 06/30/1998 |
| 5748948 | Reset signal generator The present invention relates to a reset signal generator adapted to be used with a microprocessor for generating a reset signal to initialize the microprocessor, which includes an oscillator to generate a fixed clock signal, a counter electrically connec... | 05/05/1998 |
| 5745391 | Apparatus for and method of turning on and shutting off a computing device An apparatus for and method of turning a computer on and off. A switch accepts on and off commands from a user which are transmitted to latch circuitry which, in turn, controls relay control circuitry. Relay control circuitry opens or closed a relay in re... | 04/28/1998 |
| 5737515 | Method and mechanism for guaranteeing timeliness of programs In order to prevent data corruption and inconsistency caused by incorrect assumption regarding a presumably failed node and/or program, a fail-fast timer mechanism enforces deadlines, i.e. enforces timeliness in programs. For example, given a program whic... | 04/07/1998 |
| 5724599 | Message passing and blast interrupt from processor The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decod... | 03/03/1998 |
| 5701417 | Method and apparatus for providing initial instructions through a communications interface in a multiple computer system A system for providing initial instructions to a first computer from a second computer through a communications interface connected between the two computers. A decoder causes the first computer to address the communications interface when the first compu... | 12/23/1997 |
| 5699505 | Method and system for automatically collecting diagnostic information from a computer system A method is provided for collecting information located within a plurality of hardware elements of a computer system. The hardware elements of the plurality of hardware elements are simultaneously instructed to collect the information. The information wit... | 12/16/1997 |
| 5696897 | Method and apparatus for a multi-layer system quiescent suspend and resume operation The state of a functioning computer operating system is quickly stored onto a nonvolatile storage device such that the computer system may be suspended quickly. To quickly save the state of computer operating system, a process firsts prepares for the comp... | 12/09/1997 |
| 5696895 | Fault tolerant multiple network servers A fault tolerant multiple network server system in which multiple servers concurrently act as back-up servers for each other even while they are providing their own server services to the system. Rather than having an unused server monitoring for failure ... | 12/09/1997 |
| 5689430 | Internal state determining apparatus An internal state determining apparatus according to the present invention includes at least one inner circuit, means for detecting a change in voltage supplied from an external device and outputting a detected signal in response to the change in voltage ... | 11/18/1997 |
| 5682314 | Controller apparatus for vehicle A controller apparatus for a vehicle includes a computer for controlling devices mounted in the vehicle, and a detector means for detecting the state of the computer immediately before the computer enters a reset state. The computer determines its process... | 10/28/1997 |
| 5675727 | Difference recording apparatus having a processing unit, recording unit, log update section, and log comparator using a classification key in a log of input data A difference recording apparatus includes a log comparator, a processing unit, a recording unit, and a log update section. The log comparator detects a log difference by using a classification key in a log of input data. The processing unit restores the l... | 10/07/1997 |
| 5673391 | Hardware retry trap for millicoded processor Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage ... | 09/30/1997 |
| 5657473 | Method and apparatus for controlling access to and corruption of information in computer systems An apparatus and method restrict the corruption or destruction of data held on a storage medium forming part of a computer system by hostile programs such as "viruses"by employing a "Supervisor" which controls the reading, writing and formatting of sector... | 08/12/1997 |
| 5655083 | Programmable rset system and method for computer network A network includes a plurality of computer systems interconnected by a plurality of communication links. At least one of the computer systems includes a resettable computer and a reset circuit. The reset circuit is actuable in response to the receipt of a... | 08/05/1997 |
| 5644702 | Microcomputer, microcomputer containing apparatus, and IC card A microcomputer includes a CPU, a RAM for storing data, an oscillation circuit and a battery. The CPU has a first threshold for a power supply voltage for ensuring normal operation. The oscillation circuit supplies an oscillation signal to the CPU and als... | 07/01/1997 |
| 5636341 | Fault processing method and information processing system When a fault occurs on a data communication processor that controls data communication between information processors, all information processors connected to the data communication processor are notified of the occurrence of the fault, upon which the inf... | 06/03/1997 |
| 5627962 | Circuit for reassigning the power-on processor in a multiprocessing system A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fa... | 05/06/1997 |
| 5621887 | Fault tolerant disk management system which tests failed disks during varied time intervals which are based upon the criticality associated with the failed disks A fault tolerant disk management system supports compound disks which are mirrored, so as to tolerate single point faults in any one physical disk of the compound disk. The system further minimizes the exposure of data stored on such a compound disk arisi... | 04/15/1997 |
