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| Number | Title | Issue Date |
| 8190946 | Fault detecting method and information processing apparatus An information processing apparatus including a storage area separated into a user space and a kernel space executes, generating a core file of a process existing in the user space, retaining the process with the core file which starts being generated in the user sp... | 05/29/2012 |
| 8176361 | Data processing with protection against soft errors A processing circuit has functional units (10a-c) configured to perform operations each in response to a respective command. The functional units (10a-c) are configured to execute at least one of the operations with a select... | 05/08/2012 |
| 8156370 | Computer system and method of control thereof A computer system is described having a plurality of hardware resources, a plurality of virtual partitions having allocated thereto some of those of hardware resources or parts thereof, said virtual partitions having an operating system loaded thereon, a partition m... | 04/10/2012 |
| 8117494 | DMI redundancy in multiple processor computer systems In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable base... | 02/14/2012 |
| 8108715 | Systems and methods for resolving split-brain scenarios in computer clusters A computer-implemented method for resolving split-brain scenarios in computer clusters may include (1) identifying a plurality of nodes within a computer cluster that are configured to collectively perform at least one task, (2) receiving, from a node within the com... | 01/31/2012 |
| 8108714 | Method and system for soft error recovery during processor execution A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipelin... | 01/31/2012 |
| 8095821 | Debugging for multiple errors in a microprocessor environment A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range i... | 01/10/2012 |
| 8090982 | Multiprocessor system enabling controlling with specific processor under abnormal operation and control method thereof A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specif... | 01/03/2012 |
| 8082467 | Triggering workaround capabilities based on events active in a processor pipeline A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set... | 12/20/2011 |
| 8065559 | Systems and methods for load balancing via a plurality of virtual servers upon failover using metrics from a backup virtual server The present invention provides methods and systems for performing load balancing via a plurality of virtual servers upon a failover using metrics from a backup virtual server. The methods and systems described herein provide systems and methods for an appliance dete... | 11/22/2011 |
| 8060778 | Processor controller, processor control method, storage medium, and external controller A processor having a plurality of hardware resources can perform separate controls within a proper range according to the dependent relations of hardware resources troubled. In case a notification is made of the failure of the hardware resources constituting the pro... | 11/15/2011 |
| 8055934 | Error routing in a multi-root communication fabric In one aspect of the present description, in response to detection of a failure of a root server of a storage controller, a switch for input/output adapters may be reconfigured to report errors to a successor root server without reinitializing the input/output adapt... | 11/08/2011 |
| 8055939 | Memory control device and methods thereof A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event... | 11/08/2011 |
| 8051323 | Auxiliary circuit structure in a split-lock dual processor system A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1 checks the operation of the other processor 4-0 and a... | 11/01/2011 |
| 8041992 | Input compensated and/or overcompensated computing Techniques are generally described for correcting computation errors via input compensation and/or input overcompensation. In various examples, errors of a computation may be detected, and input compensation and/or overcompensation to correct the errors may be creat... | 10/18/2011 |
| 8041986 | Take over method for computer system A proposed fail over method for taking over task that is preformed on an active server to a backup server, even when the active server and the backup server have different hardware configuration. The method for making a backup server take over task when a fault occu... | 10/18/2011 |
| 8037445 | System for and method of controlling a VLSI environment An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of th... | 10/11/2011 |
| 8024604 | Information processing apparatus and error processing An information processing apparatus includes a first processing unit, a second processing unit, and a common storage unit that is commonly accessed by the first processing unit and the second processing unit. The first processing unit writes a request in the common ... | 09/20/2011 |
| 8020038 | System and method for adjusting operating points of a processor based on detected processor errors A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a p... | 09/13/2011 |
| 8020039 | Recovering from errors in streaming DSP applications A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error ... | 09/13/2011 |
| 8020040 | Information processing apparatus for handling errors In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error handler program stored in a first memory that is one of a number of memories. If the first processor fails in co... | 09/13/2011 |
| 8010838 | Hardware recovery responsive to concurrent maintenance Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system ... | 08/30/2011 |
| 8006129 | Detecting and preventing the split-brain condition in redundant processing units In an example embodiment the occurrence of the split-brain condition in a High-Availability system, having active and standby processing units, is detected, its cause is diagnosed, and the cause is treated to prevent interruption of service. Diagnosis and treatment ... | 08/23/2011 |
| 7996713 | Server-to-server integrity checking A method performed by a primary server includes receiving integrity criteria and sending a health check request to a secondary server based on the received integrity criteria. The method also includes receiving integrity information from the secondary server and che... | 08/09/2011 |
| 7975172 | Redundant execution of instructions in multistage execution pipeline during unused execution cycles A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the exec... | 07/05/2011 |
| 7975167 | Information system An information system includes a housing with a plurality of units mounted thereon, a communication path built in the housing to take charge of information communication between a plurality of the units mounted on the housing, an information unit mounted on the hous... | 07/05/2011 |
| 7966519 | Reconfiguration in a multi-core processor system with configurable isolation Methods and integrated circuits for reconfiguration in a multi-core processor system with configurable isolation are described. According to one embodiment, a processor configuration method includes determining that a first module is faulty. A second module is confi... | 06/21/2011 |
| 7958392 | Assigning a processor to a logical partition Assigning a processor to a logical partition in a computer supporting multiple logical partitions that include assigning priorities to partitions, detecting a checkstop of a failing processor of a partition, retrieving the failing processor's state, replacing by a h... | 06/07/2011 |
| 7945811 | Low power, high reliability specific compound functional units To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one function... | 05/17/2011 |
| 7937615 | Method for improving reliability of multi-core processor computer In a system including a plurality of multi-core processors, a table for managing the processors and cores owned by the processors is provided and a single virtual server is formed by using cores owned by different processors when generating the virtual server. Accor... | 05/03/2011 |
| 7904751 | System abstraction layer, processor abstraction layer, and operating system error handling Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes ... | 03/08/2011 |
| 7900085 | Backup coordinator for distributed transactions A primary coordinator generates a prepare message for a two-phase commit distributed transaction, the prepare message including an address of a backup coordinator. The primary coordinator maintains a transaction log of the distributed transaction, wherein the transa... | 03/01/2011 |
| 7895469 | Integrated circuit using speculative execution An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first ... | 02/22/2011 |
| 7895468 | Autonomous takeover destination changing method in a failover For realizing an optimum failover in NAS, this invention provides a computer system including: a first computer; a second computer; a third computer; and a storage device coupled to the plurality of computers via a network, in which: the first computer executes, upo... | 02/22/2011 |
| 7890797 | Vehicle including a processor system having fault tolerance A vehicle includes a high assurance processing system including a plurality of data processors coupled in parallel, a bridge coupled to the input/output processor, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor d... | 02/15/2011 |
| 7873868 | Method for obtaining higher throughput in a computer system utilizing a clustered systems manager An apparatus for and method of enhancing reliability and performance within a cluster lock processing system having a relatively large number of commodity instruction processors which are managed by a highly scalable, off the shelf platform. Because the commodity pr... | 01/18/2011 |
| 7865769 | In situ register state error recovery and restart mechanism Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of... | 01/04/2011 |
| 7827442 | Shelf management controller with hardware/software implemented dual redundant configuration A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in ... | 11/02/2010 |
| 7827443 | Processor instruction retry recovery Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the pro... | 11/02/2010 |
| 7823012 | Autonomically adjusting configuration parameters for a server when a different server fails A load balancer detects a server failure, and sends a failure notification message to the remaining servers. In response, one or more of the remaining servers may autonomically adjust their configuration parameters, thereby allowing the remaining servers to better h... | 10/26/2010 |
