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| Number | Title | Issue Date |
| 8181059 | Inter-processor communication channel including power-down functionality Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication... | 05/15/2012 |
| 8060771 | Glitch-free clock suspend and resume circuit Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a... | 11/15/2011 |
| 8020027 | Timing control in a specialized processing block The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline registers within the specialized processing block. Th... | 09/13/2011 |
| 7975164 | DDR memory controller A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR me... | 07/05/2011 |
| 7930582 | Image processing apparatus and method of transmitting reference clock An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the control unit and transmitted to the engine unit via the interface. On... | 04/19/2011 |
| 7752483 | Process and system for three-dimensional urban modeling A Heart Beat System (HBS) enables both inertial navigation system (INS) technology and other sensors, e.g., laser radar (LIDAR) systems, cameras and the like to be precisely time-coupled. The result of this coupling enables microsecond control by the HBS to each sen... | 07/06/2010 |
| 7581133 | System and method of providing real time to devices within a server chassis An information management system is disclosed and can include a server chassis having a chassis control panel. The chassis control panel can include a real time clock. Further, the system can include a chassis management controller connected to the chassis control p... | 08/25/2009 |
| 7444529 | Microcomputer having rewritable nonvolatile memory A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the... | 10/28/2008 |
| 7444533 | Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by ... | 10/28/2008 |
| 7437584 | Apparatus and method for reducing power consumption in electronic devices An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal bas... | 10/14/2008 |
| 7421607 | Method and apparatus for providing symmetrical output data for a double data rate DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, arr... | 09/02/2008 |
| 7421606 | DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x ... | 09/02/2008 |
| 7409568 | Power supply voltage droop compensated clock modulation for microprocessors A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected. ... | 08/05/2008 |
| 7403122 | RFID tag circuits operable at different speeds Embodiments of RFID tag circuits and methods are described, which include a chip having a clock circuit operable to generate a clock signal having different frequencies, and one or more components operable to work at the different frequencies. In addition to a regul... | 07/22/2008 |
| 7395449 | Method and apparatus for limiting processor clock frequency A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a sign... | 07/01/2008 |
| 7380152 | Daisy chained multi-device system and operating method A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the dais... | 05/27/2008 |
| 7376856 | Circuit arrangement An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for receiving a pulse of a clock signal (CK) to introduce d... | 05/20/2008 |
| 7376857 | Method of timing calibration using slower data rate pattern An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the d... | 05/20/2008 |
| 7373536 | Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A speci... | 05/13/2008 |
| 7370191 | Method and device for playing compressed multimedia files in semi-power on state of a computer A method and device for playing compressed multimedia files in a semi-power on state of a computer is provided. A program is provided in the BIOS so that POST (Power On Self Test) is not performed after the power is turned on. The program directly initializes multim... | 05/06/2008 |
| 7366938 | Reset in a system-on-chip circuit An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated cir... | 04/29/2008 |
| 7366937 | Fast synchronization of a number of digital clocks The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, resp... | 04/29/2008 |
| 7363408 | Interruption control system and method An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a ... | 04/22/2008 |
| 7360220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two di... | 04/15/2008 |
| 7356630 | Processor control device for stopping processor operation A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module,... | 04/08/2008 |
| 7356726 | Frequency control apparatus for controlling the operation frequency of an object A frequency control apparatus and an information processing apparatus includes an observation section for observing an operation state of a control object which operates with a variably controlled frequency, a frequency determination section for determining a clock ... | 04/08/2008 |
| 7350096 | Circuit to reduce power supply fluctuations in high frequency/ high power circuits The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to ... | 03/25/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7340631 | Drift-tolerant sync pulse circuit in a sync pulse generator A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock do... | 03/04/2008 |
| 7340625 | Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance ... | 03/04/2008 |
| 7340624 | Clock control system and clock control method This invention relates to a clock control system including a CPU, a peripheral functional block for the CPU, a frequency multiplication circuit which multiplies the frequency of an input system clock and outputs the multiplied system clock, a plurality of frequency ... | 03/04/2008 |
| 7337347 | Information processing system and method for timing adjustment An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of vari... | 02/26/2008 |
| 7334148 | Optimization of integrated circuit device I/O bus timing The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting... | 02/19/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7325152 | Synchronous signal generator A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the ... | 01/29/2008 |
| 7321980 | Software power control of circuit modules in a shared and distributed DMA system A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bi... | 01/22/2008 |
| 7320065 | Multithread embedded processor with input/output capability An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with superv... | 01/15/2008 |
| 7310751 | Timeout event trigger generation A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system als... | 12/18/2007 |
| 7302601 | Device and method for synchronizing an exchange of data with a remote member A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock sig... | 11/27/2007 |
| 7302518 | Method and system for managing a suspend request in a flash memory System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspe... | 11/27/2007 |
