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Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8176352 | Clock domain data transfer device and methods thereof Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each c... | 05/08/2012 |
| 8176353 | Method for the data transfer between at least two clock domains The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2), comprising the following for the transfer of data from the ... | 05/08/2012 |
| 8176354 | Wave pipeline with selectively opaque register stages A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal stages that are normally transparent. A programmable local clock control c... | 05/08/2012 |
| 8171336 | Method for protecting a secured real time clock module and a device having protection capabilities A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking t... | 05/01/2012 |
| 8161314 | Method and system for analog frequency clocking in processor cores A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequen... | 04/17/2012 |
| 8151134 | SPI devices and method for transferring data between the SPI devices A method for transferring data between a serial peripheral interface (SPI) master device and an SPI slave device generates a first clock signal for the SPI master device and a second clock signal for the SPI slave device. Clock frequency of the first clock signal an... | 04/03/2012 |
| 8122279 | Multiphase clocking systems with ring bus architecture Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus ha... | 02/21/2012 |
| 8099621 | Data reception apparatus and microcomputer having the same A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature ... | 01/17/2012 |
| 8086892 | Microcode configurable frequency clock A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the des... | 12/27/2011 |
| 8065553 | Phase interpolator for a timing signal generating circuit A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRA... | 11/22/2011 |
| 8055932 | Precision oscillator for an asynchronous transmission system A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associat... | 11/08/2011 |
| 8028187 | Dual-mode communication apparatus and power management method thereof A dual-mode communication apparatus and a method thereof are provided. The dual-mode communication apparatus comprises a microprocessor, a first tick generator, a second tick generator, and an operation system tick module that comprises a tick converter and an OS ti... | 09/27/2011 |
| 8015428 | Processing device and clock control method A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock genera... | 09/06/2011 |
| 8015429 | Clock and data recovery (CDR) method and apparatus Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (D... | 09/06/2011 |
| 8015427 | System and method for prioritization of clock rates in a multi-core processor A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either internal to the processor or operatively inter... | 09/06/2011 |
| 8001412 | Combined alignment scrambler function for elastic interface An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambl... | 08/16/2011 |
| 7996704 | Asynchronous first in first out interface and operation method thereof The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock control... | 08/09/2011 |
| 7996705 | Signal bus, multilevel input interface and information processor A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, inc... | 08/09/2011 |
| 7984321 | Data transfer control device and electronic instrument A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generat... | 07/19/2011 |
| 7979732 | Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock contr... | 07/12/2011 |
| 7975163 | Apparatus and method for masking a clock signal A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock source. In one version, a memory controller configures a masking circ... | 07/05/2011 |
| 7966512 | Data processing device and mobile device A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is pro... | 06/21/2011 |
| 7958383 | Computer system with adjustable data transmission rate A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data tr... | 06/07/2011 |
| 7945806 | Data processing apparatus and method for controlling a transfer of payload data over a communication channel A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associate... | 05/17/2011 |
| 7937607 | Asynchronous data holding circuit An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enab... | 05/03/2011 |
| 7937608 | Clock generating circuit and digital circuit system incorporating the same A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and reg... | 05/03/2011 |
| 7937606 | Shadow unit for shadowing circuit status Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to... | 05/03/2011 |
| 7930581 | Automation device The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one ... | 04/19/2011 |
| 7921322 | Optimize personalization conditions for electronic device transmission rates with increased transmitting frequency Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the determination of different clock frequencies that an electronic device(s) ca... | 04/05/2011 |
| 7917799 | Method and system for digital frequency clocking in processor cores Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable freq... | 03/29/2011 |
| 7908509 | Method and apparatus for controlling an upper layer in a protocol stack to delay timeouts In a device communicating over a network, a proxy to delay timeout of an application on the device where the proxy is on a communications path between the application and the network, the proxy comprising means for registering a data request from the application to ... | 03/15/2011 |
| 7908508 | Low power method of responsively initiating fast response to a detected change of condition A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state ... | 03/15/2011 |
| 7900081 | Microcomputer and control system having the same A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that oper... | 03/01/2011 |
| 7886179 | Method for adjusting working frequency of chip A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full screen mode is executed, and a control hot key is enabled. Afterwards,... | 02/08/2011 |
| 7882385 | Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may ... | 02/01/2011 |
| 7856571 | Method and system for communication employing dual slew rates A bus for implementation with a computer system, as well as a computer processing device capable of interacting with such a bus, and a method of communicating signals over a bus, are disclosed. In at least one embodiment, the bus is a processor bus that includes a f... | 12/21/2010 |
| 7836326 | Apparatus with variable pipeline stages via unification processing and cancellation To satisfy a required processing speed and achieve the maximum power-saving effect in a microprocessor. A control value is calculated by performing proportional and integral processing on a deviation of a target instruction execution number from a measured instructi... | 11/16/2010 |
| 7836327 | Signal processing circuit for accessing a memory based on adjustable memory control clock A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory... | 11/16/2010 |
| 7827433 | Time-multiplexed routing for reducing pipelining registers Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the... | 11/02/2010 |
| 7823004 | Clock source selection for modular computer system as a function of modulo difference A computer system provides for connecting consecutively positioned modules to operate collectively as server. Each module calculates a modulo difference between its position and that of a module serving as a clock source; each module selects a clock input as a funct... | 10/26/2010 |
