Class 713/503 - Correction for skew, phase, or rate

Subclass of Class 713 - Electrical computers and digital processing systems: support
Definition: Subject matter wherein a timing interval is corrected for
No. of patents: 937
Last issue date: 05/15/2012

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Number	Title	Issue Date
8181058	Clock-data-recovery technique for high-speed links A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal...	05/15/2012
8171335	Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a ...	05/01/2012
8161313	Serial-connected memory system with duty cycle correction Systems and methods for correcting clock duty cycle are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in tu...	04/17/2012
8140885	Accounting for microprocessor resource consumption Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling thi...	03/20/2012
8135978	Performing a perform timing facility function instruction for sychronizing TOD clocks A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system com...	03/13/2012
8132040	Channel-to-channel deskew systems and methods Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includ...	03/06/2012
8132041	Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is c...	03/06/2012
8127172	Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI...	02/28/2012
8122278	Clock skew measurement for multiprocessor systems Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize...	02/21/2012
8117485	Memory system for seamless switching Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first thr...	02/14/2012
8108710	Differential communication link with skew compensation circuit A system and method is presented for reducing skew between the positive and negative components of a differential signal in a high speed communications link. The communications link includes a signal generator producing and transmitting complementary positive and ne...	01/31/2012
8090973	Skew management in an interconnection system An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data la...	01/03/2012
8051320	Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined ...	11/01/2011
8041983	Method and apparatus for improving data transfer A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the tra...	10/18/2011
8037340	Apparatus and method for micro performance tuning of a clocked digital system An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, th...	10/11/2011
8028186	Skew management in an interconnection system An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data la...	09/27/2011
8024599	Bias and random delay cancellation A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using ...	09/20/2011
8020026	Phase-aligning corrected and uncorrected clocks The present invention relates to providing a system clock signal that is based on either a first clock signal that is capable of being frequency-corrected or a second clock signal that is not capable of being frequency-corrected, depending on system needs. When the ...	09/13/2011
8010825	Jitter reduction circuit A jitter reduction circuit includes a signal line transmitting a first signal and having a plurality of sections, and a plurality of delay lines transmitting a second signal and provided in one-to-one correspondence to the sections of the signal line, wherein the pl...	08/30/2011
7971088	Clock skew controller and integrated circuit including the same A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first ...	06/28/2011
7954001	Nibble de-skew method, apparatus, and system De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits. ...	05/31/2011
7941689	Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by fi...	05/10/2011
7937605	Method of deskewing a differential signal and a system and circuit therefor A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data chan...	05/03/2011
7921321	Automatic clock and data alignment A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts ...	04/05/2011
7917798	Superconducting digital phase rotator An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. ...	03/29/2011
7913104	Method and apparatus for receive channel data alignment with minimized latency variation Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is ...	03/22/2011
7886178	Semiconductor memory apparatus In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has ...	02/08/2011
7870415	Clock processors in high-speed signal converter systems with data clock aligner sharing error signal produced in duty cycle stabilizer Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its op...	01/11/2011
7870414	Clock tree circuit and semiconductor memory device using the same, and duty cycle correction method A semiconductor memory device, which includes a clock tree circuit for correcting the duty cycle of a clock. The device sets a beta ratio to cause a constant duty cycle by using a reference clock having a constant duty cycle in a test mode, and then applies the set ...	01/11/2011
7865760	Use of T4 timestamps to calculate clock offset and skew Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer sy...	01/04/2011
7827432	Phase frequency detector with limited output pulse width and method thereof Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first...	11/02/2010
RE41752	Bus clock controlling apparatus and method The present invention relates to an apparatus and method for throttling a clock of a bus used for data exchange between devices in a computer such as a portable computer or notebook. Methods according to the invention can set a throttle rate of a clock to a predeter...	09/21/2010
7770049	Controller for clock skew determination and reduction based on a lead count over multiple clock cycles Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signa...	08/03/2010
7765425	Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for cl...	07/27/2010
7765424	System and method for injecting phase jitter into integrated circuit test signals A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock signal is provided for each of the pin groups to generate respective delayed clock signals. The phase shift p...	07/27/2010
7747892	System for automatically selecting intermediate power supply voltages for intermediate level shifters The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal...	06/29/2010
7721137	Bus receiver and method of deskewing bus signals A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and ...	05/18/2010
7716516	Method for controlling operation of microprocessor which performs duty cycle correction process A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle c...	05/11/2010
7702946	Digital clock filter circuit for a gapped clock of a non-isochronous data signal having a selected one of at least two nominal data rates A clock filter circuit (20), which serves for filtering the clock of non-isochronous data signals having a selected one of at least two nominal data rates, has an auxiliary clock source (21) that generates an auxiliary clock signal (27) with a p...	04/20/2010
7681063	Clock data recovery circuit with circuit loop disablement A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the trans...	03/16/2010

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Class 713/503 - Correction for skew, phase, or rate