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| Number | Title | Issue Date |
| 8185774 | Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m ... | 05/22/2012 |
| 8185772 | Determining execution times of commands Methods and apparatuses for determining a number of clock cycles during an execution of a command by a processor, determining a value associated with the number of clock cycles, storing an indicator indicative of the command, responsive to the value indicative of th... | 05/22/2012 |
| 8185773 | Processor system employing a signal acquisition managing device and signal acquisition managing device A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and gene... | 05/22/2012 |
| 8156366 | Method and apparatus for timing and event processing in wireless systems A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller... | 04/10/2012 |
| 8140883 | Scheduling of pipelined loop operations Pipelined loop operations are efficiently scheduled. A preliminary as soon as possible (ASAP) schedule for a data operation in a pipelined loop is determined. A producer operation clock cycle associated with a producer operation in the pipelined loop is determined. ... | 03/20/2012 |
| 8140884 | Efficient time-based memory counters Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of predefined time intervals. Furthermore, a set of pointers may be used to r... | 03/20/2012 |
| 8108709 | Output enable signal generation circuit for semiconductor memory device A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clo... | 01/31/2012 |
| 8046624 | Propagation of viruses through an information technology network Requests to send data from a first host within a network of hosts are monitored against a record of destination hosts who have been sent data in accordance with a predetermined policy. Destination host identities not the record are stored in a buffer. The buffer siz... | 10/25/2011 |
| 8020024 | Method for preventing erroneous resetting of electronic device due to electrostatic discharge An exemplary method for preventing an electronic device from erroneously resetting due to electrostatic discharge (ESD) involves an electronic device that includes a reset control pin. The method includes providing a timer, and setting a reset condition of the reset... | 09/13/2011 |
| 8020025 | Power saving scheduler for timed events The disclosed system and methods include a power saving scheduler that maintains timed events in an event table. Each timed event has an associated tolerance period within which the event should begin execution following a trigger, and a timestamp indicating a sched... | 09/13/2011 |
| 7996703 | Method and apparatus to avoid power transients during a microprocessor test Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor.... | 08/09/2011 |
| 7984320 | Silent time tampering detection Computers and other electronic devices typically include a timing operation such as a clock in an operating system. It is anticipated that hackers may tamper with this clock. This tampering might be especially advantage in the context of systems which provide for re... | 07/19/2011 |
| 7954000 | Power supply current spike reduction techniques for an integrated circuit An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clo... | 05/31/2011 |
| 7949891 | Timer circuit storing a plurality of time measurements with different sets of measurement time that can be realized by starting the time measurements asynchronously A timer circuit for a mobile communication terminal includes a counter operating under a reference clock, a storage unit that stores a timer timeout time corresponding to a time measurement request when receiving the time measurement request from a CPU, and a compar... | 05/24/2011 |
| 7941688 | Managing timers in a multiprocessor environment Timers are managed in a multiprocessing environment. Some timers are local to a given logical processor; such a local timer is inserted on and will be canceled only from that logical processor. Other timers are global to a logical processor. A global timer which was... | 05/10/2011 |
| 7941687 | Method and apparatus for digital I/O expander chip with multi-function timer cells A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved thr... | 05/10/2011 |
| 7921320 | Single wire serial interface A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed... | 04/05/2011 |
| 7886177 | Method and apparatus of collecting timer ticks Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embo... | 02/08/2011 |
| 7844850 | Broadcast/VOD receiver and viewing management method According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main progra... | 11/30/2010 |
| 7836325 | Power consumption reduction and quicker interruption response in an information processing device utilizing a first timer and a second timer wherein the second timer is only conditionally activated An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a ... | 11/16/2010 |
| 7823002 | Digital reliability monitor having autonomic repair and notification capability An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when... | 10/26/2010 |
| 7783912 | Sequencing control circuit A sequencing control circuit includes a chip (30), a first control circuit (10), a second control circuit (20), and a lagging voltage terminal (700). The chip is connected to a first voltage terminal (100) and a second voltage term... | 08/24/2010 |
| 7779288 | High resolution timer circuit and time count method for suppressing increase in storage capacity A timer circuit includes a storage unit to store a series of first data content relating to a time into a specified address area, a target value generation unit to read the first data content from a read address of the storage unit and to generate, as a target value... | 08/17/2010 |
| 7779289 | Methods and data processing systems for sharing a clock between non-secured and secured tasks A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of th... | 08/17/2010 |
| 7770048 | Calculating and indicating a number of times a device is inserted into a slot An apparatus is disclosed. The apparatus comprises a device and a counter system coupled thereto. The counter system provides an indication of a number of times the device is inserted into a slot. Through the use of the device disclosed above, a history and a number... | 08/03/2010 |
| 7765423 | Implementation of multiple clock interfaces A method for implementing multiple clock interfaces in a single media player. The method and accompanying device are configured to utilize the preferred secure clock. If the remote host cannot support a secure clock, the method can alternately implement an anti-roll... | 07/27/2010 |
| 7761729 | Delay compensation Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal. ... | 07/20/2010 |
| 7752481 | Information processing apparatus and resume control method According to one embodiment, there is provided an information processing apparatus, including a first clock portion to output a first signal when a measurement value coincides with first set time, a second clock portion to output a second signal when a measurement v... | 07/06/2010 |
| 7725758 | Multifunctional timer/event counter device and method of using such a device A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module inclu... | 05/25/2010 |
| 7590880 | Circuitry and method for detecting and protecting against over-clocking attacks The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for providing a delayed signal of the test signal, and circuitry for compari... | 09/15/2009 |
| 7571341 | Method and system for fast frequency switch for a power throttle in an integrated device The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor. ... | 08/04/2009 |
| 7543173 | Timestamp generator A method of generating a timestamp includes measuring a time period between two events, automatically determining a precision for an indication of the time period, and storing the timestamp. The precision for the indication of the time period is decreased as the tim... | 06/02/2009 |
| 7539890 | Hybrid computer security clock A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every read of the monotonic time from the clock object. The clock object can also include an indication of a le... | 05/26/2009 |
| 7536580 | System and method for generating timer output corresponding to timer request from plurality of processes The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves efficient timer generation. The present invention includes a count setting unit (register) presetting a timer va... | 05/19/2009 |
| 7529961 | Semiconductor device with clock failure detection circuitry A semiconductor device is composed of an oscillator circuit developing a clock, and an oscillation failure detect unit. The an oscillation failure detect unit is configured to obtain at least one count value through counting clock pulses of the clock, and to activat... | 05/05/2009 |
| 7519846 | Detection of an in-band reset Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is cou... | 04/14/2009 |
| 7512829 | Real time event stream processor to ensure up-to-date and accurate result Identifying a transaction from a real time event stream having latency. A method of the invention receives events from the real time event stream where events define a plurality of transactions to be identified. Each of the transactions includes a first event and a ... | 03/31/2009 |
| 7500130 | Cycle-accurate real-time clocks and methods to operate the same Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a selectively-operable clock, a multiplexer to select from at least an output signal associated with the first coun... | 03/03/2009 |
| 7475271 | Exponential channelized timer A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, ... | 01/06/2009 |
| 7444533 | Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by ... | 10/28/2008 |
