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| Number | Title | Issue Date |
| 8132039 | Techniques for generating clock signals using counters The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count si... | 03/06/2012 |
| 8117484 | Method and device for generation of out-of-phase binary signals, and use of the same A method for the generation of binary signals (So1, So2, So3) which are out-of-phase with a control phase angle (?) which is continuously variable in relation to at least one synchronisation binary signal from a set of synchronisation binary sig... | 02/14/2012 |
| 8108708 | Power optimization when using external clock sources Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be pro... | 01/31/2012 |
| 8095818 | Method and apparatus for on-demand power management An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing s... | 01/10/2012 |
| 8086891 | Power management of components having clock processing circuits A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied t... | 12/27/2011 |
| 8078901 | Method for increasing a processor operating frequency when other subsystem demands are low A host activity measure indicative of a frequency of disk access commands received by a disk drive is determined, and then compared against a host activity threshold. A subsystem activity measure indicative of an activity level of a disk drive subsystem is also dete... | 12/13/2011 |
| 8037339 | Security device intended to be connected to a processing unit for an audio/video signal and process using such a device Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined communication protocols. The security device may further include a freque... | 10/11/2011 |
| 8024598 | Apparatus and method for clock generation with piecewise linear modulation An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile consisting of t... | 09/20/2011 |
| 8006115 | Central processing unit with multiple clock zones and operating method One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to th... | 08/23/2011 |
| 8001411 | Generating a local clock domain using dynamic controls A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clo... | 08/16/2011 |
| 7996702 | System and method for testing overclocking capability of CPU A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module... | 08/09/2011 |
| 7996701 | Automated clock relationship detection Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detect... | 08/09/2011 |
| 7966511 | Power management coordination in multi-core processors Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power poli... | 06/21/2011 |
| 7945805 | Architecture for a physical interface of a high speed front side bus A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graph... | 05/17/2011 |
| 7945804 | Methods and systems for digitally controlled multi-frequency clocking of multi-core processors A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a r... | 05/17/2011 |
| 7945803 | Clock generation for multiple clock domains This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments o... | 05/17/2011 |
| 7934115 | Deriving clocks in a memory system A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating... | 04/26/2011 |
| 7917797 | Clock generation using a fractional phase detector Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output ... | 03/29/2011 |
| 7913103 | Method and apparatus for clock cycle stealing A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received ref... | 03/22/2011 |
| 7895461 | Clock shifting and prioritization system and method A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device.... | 02/22/2011 |
| 7882384 | Setting and minimizing a derived clock frequency based on an input time interval An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS′... | 02/01/2011 |
| 7865759 | Programmable clock control architecture for at-speed testing According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The N-stage programmable clock control architecture further includes means f... | 01/04/2011 |
| 7853819 | Method and device for clock changeover in a multi-processor system A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover i... | 12/14/2010 |
| 7849349 | Reduced-delay clocked logic Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic cir... | 12/07/2010 |
| 7827431 | Memory card having memory device and host apparatus accessing memory card A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatu... | 11/02/2010 |
| 7809974 | Circuit to reduce power supply fluctuations in high frequency/high power circuits A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counte... | 10/05/2010 |
| 7805628 | High resolution clock signal generator A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal wit... | 09/28/2010 |
| 7761728 | Apparatus, system, and method for resetting an inter-integrated circuit data line with a clock line An apparatus, system, and method are disclosed for resetting an inter-integrated circuit data line with a clock line. A hang module detects that a data line that carries data between an I2C bus master and an I2C bus slave is hung, wherein the I2C bus master and I2C ... | 07/20/2010 |
| 7752480 | System and method for switching digital circuit clock net driver without losing clock pulses A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the devic... | 07/06/2010 |
| 7739536 | Intelligent frequency and voltage margining A system and method for voltage and frequency margining of a digital system such as a digital processing system. Various implementations of the present invention may be utilized to programmatically vary the voltage and or frequency utilized by one or more components... | 06/15/2010 |
| 7725757 | Method and system for fast frequency switch for a power throttle in an integrated device In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the counter may be a control logic to generate a control signal to change from ... | 05/25/2010 |
| 7725756 | Method for generating programmable data rate from a single clock A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding the delta to a previous accumulative offset for each clock period of th... | 05/25/2010 |
| 7702945 | Semiconductor device and communication control method The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and hi... | 04/20/2010 |
| 7694164 | Operating system-independent method and system of determining CPU utilization A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals. ... | 04/06/2010 |
| 7685458 | Assigned task information based variable phase delayed clock signals to processor cores to reduce di/dt Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor c... | 03/23/2010 |
| 7661011 | Method and apparatus for a variable processing period in an integrated circuit The invention is a system for modifying the processing period in a digital logic module. The invention comprises the following. A processing circuit is configured to receive an input in order to create an output. A controller is coupled to the processing circuit and... | 02/09/2010 |
| 7657775 | Dynamic memory clock adjustments Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selecte... | 02/02/2010 |
| 7640449 | Systems and methods for dynamic clock frequencies for low power design Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without alter... | 12/29/2009 |
| 7634678 | Application software initiated speedup An instruction, processor, system, and method allow application level software to explicitly request a temporary performance boost, from computing hardware. Advanced management of a working frequency of a processor achieves the performance boost. Preferably, a proce... | 12/15/2009 |
| 7624297 | Architecture for a physical interface of a high speed front side bus A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor. ... | 11/24/2009 |
