Class 713/500 - CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS

Subclass of Class 713 - Electrical computers and digital processing systems: support
Definition: Subject matter including generation, division or distribution
No. of patents: 1657
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190943	Systolic merge sorter A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to su...	05/29/2012
8190944	Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal....	05/29/2012
8185771	Clock generation for memory access without a local oscillator A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a metho...	05/22/2012
8185770	Method for processing time values in a computer or programmable machine Modern computers (10, 20) come with different timers having different attributes like time resolution, supported time range and time reference. Some are local timers, representing relative time values like the TSC counter (11, 21) counting CPU cycles f...	05/22/2012
8171332	Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random ...	05/01/2012
8171333	Sub-beam forming transmitter circuitry for ultrasound system Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals. ...	05/01/2012
8171331	Memory channel having deskew separate from redrive A memory agent may have a redrive circuit having a plurality of redrive paths, and a deskew circuit separate from the plurality of redrive paths. A deskew circuit may be integral with or separate from a redrive circuit having the plurality of redrive paths. A deskew...	05/01/2012
8171334	Apparatus and method to interface two different clock domains A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed betwee...	05/01/2012
8166334	Redriver with two reference clocks and method of operation thereof A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade use...	04/24/2012
8161312	Processing data using multiple levels of power control An apparatus and method is provided for data processing where power is automatically controlled with a feed back loop with the host processor based on the internal work load characterized by performance counters. The host automatically adjusts internal frequencies o...	04/17/2012
8161311	Apparatus and method for redundant and spread spectrum clocking An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is prov...	04/17/2012
8156365	Data reception apparatus A data reception apparatus is disclosed. The data reception apparatus includes a strobe extractor for receiving a transmission signal and extracting a strobe signal from the transmission signal, the transmission signal including the strobe signal inserted between da...	04/10/2012
8145935	Clock signal generator for generating stable clock signal, semiconductor memory device including the same, and methods of operating A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses ...	03/27/2012
8135976	Modulated clock, an IC including the modulated clock and a method of providing a modulated clock signal for power control A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a d...	03/13/2012
8135977	Process for digital, bidirectional data transmission The invention relates to a process for digital, bidirectional data transmission between a processing unit and a position encoder, as based on the transmission of frames of a predetermined bit length, such that each frame is provided with at least an initial bit leng...	03/13/2012
8132037	Apparatus and method for processing wirelessly communicated data and clock information within an electronic device An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14) may include a first processor (18) that controls only wireless communications with ...	03/06/2012
8132038	System and method for calibrating a time of day (TOD) clock in a computing system node provided in a multi-node network A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for e...	03/06/2012
8122276	Apparatus and method for dynamic clock control in a pipeline system An apparatus and method for dynamically controlling a clock signal in a pipeline system are provided. In the apparatus and method, a clock generator outputs the clock signal at every period, a PDR is included with each stage for outputting information about a proces...	02/21/2012
8122277	Clock distribution chip In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock o...	02/21/2012
8117482	Timer unit circuit having plurality of output modes and method of using the same First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode,...	02/14/2012
8117483	Method to calibrate start values for write leveling in a memory system A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the p...	02/14/2012
8112655	Mesosynchronous data bus apparatus and method of data transmission A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a d...	02/07/2012
8112654	Method and an apparatus for providing timing signals to a number of circuits, and integrated circuit and a node A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal befo...	02/07/2012
8112656	Clock distribution chip In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first an...	02/07/2012
8103897	Clock generation circuit and semiconductor device including the same Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a receiving circuit, stabilized communication is possible; and to provide a semi...	01/24/2012
8103898	Explicit skew interface for mitigating crosstalk and simultaneous switching noise Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree inp...	01/24/2012
8099620	Domain crossing circuit of a semiconductor memory apparatus A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock ...	01/17/2012
8099619	Voltage regulator with drive override Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When ...	01/17/2012
8086890	Virtual machine monitor, virtual machine system and clock distribution method thereof A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock re...	12/27/2011
8086889	Semiconductor integrated circuit device for scan testing A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the cloc...	12/27/2011
8078900	Asynchronous absorption circuit with transfer performance optimizing function A selector is provided so that any one of a plurality of asynchronous absorption paths can be selected when it is assumed that operating frequencies of preceding and succeeding clock domains vary depending on the application. By an operation of a selector control ci...	12/13/2011
8078999	Structure for implementing speculative clock gating of digital logic circuits A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline st...	12/13/2011
8074096	Semiconductor integrated circuit, memory system, memory controller and memory control method Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data te...	12/06/2011
8065552	Clock generation circuit, recording device and clock generation method A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generate...	11/22/2011
8055931	Method for switching between two redundant oscillator signals within an alignment element A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the...	11/08/2011
8046622	Dynamically scaling apparatus for a system on chip power voltage A system for dynamically scaling a power voltage including a system on chip (SoC) and a power control circuit. The SoC includes a plurality of application circuits. The SoC is configured to generate internal clock signals in response to an externally supplied clock ...	10/25/2011
8046623	Timing recovery apparatus and method thereof A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a parser and a compensator. The clock generator generates a clock signal....	10/25/2011
8046621	Method and system for generation of signals up to extremely high frequencies using a delay block Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be delayed, via at least a portion of a plurality of delay elements and via a variable capacitance, to genera...	10/25/2011
8041980	Time certifying server, reference time distributing server, time certifying method, reference time distributing method, time certifying program, and communication protocol program A time certifying server has a clock unit that outputs time information. Units of time equal to or larger than a predetermined unit are acquired from the time information. Units of time from the time information smaller than the predetermined unit are corrected usin...	10/18/2011
8041981	Synchronizing timing domains based on state variables Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This sync...	10/18/2011

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Class 713/500 - CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS