Bizarre Patents
A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7184352 | Memory system and method using ECC to achieve low power refresh Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndr... | 02/27/2007 |
| 7184325 | Input circuit for memory device An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus im... | 02/27/2007 |
| 7185239 | On-chip timing characterizer An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determi... | 02/27/2007 |
| 7181636 | Method of ensuring synchronous presentation of additional data with audio data recorded on a rewritable recording medium A recording medium and a method and apparatus for managing data are provided. The method includes recording additional data in a data file separate from a file containing main data and recording navigation information that links the main data and the additional data... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7181638 | Method and apparatus for skewing data with respect to command on a DDR interface An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon... | 02/20/2007 |
| 7180522 | Apparatus and method for distributed memory control in a graphics processing system A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memor... | 02/20/2007 |
| 7180823 | Flexible SDRAM clocking (MS-DLL) A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop inc... | 02/20/2007 |
| 7180353 | Apparatus and method for low power clock distribution A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swin... | 02/20/2007 |
| 7181639 | Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, an... | 02/20/2007 |
| 7181644 | Method for synchronizing data utilized in redundant, closed loop control systems A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes... | 02/20/2007 |
| 7178113 | Identification of an integrated circuit from its physical manufacture parameters The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output termina... | 02/13/2007 |
| 7178001 | Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control sign... | 02/13/2007 |
| 7177205 | Distributed loop components In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particul... | 02/13/2007 |
| 7178048 | System and method for signal synchronization based on plural clock signals A system includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency. The strobe signal is synchronized with the data signal based on a second clock ... | 02/13/2007 |
| 7174474 | Distributed autonomous control system for multi-axis motion control A distributed multi-axis motion control system comprises a multicast communications network having several node components. Each of the node components includes a clock and an actuator. The actuators are part of a motor system and a pattern profile table of the moto... | 02/06/2007 |
| 7174521 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 02/06/2007 |
| 7173877 | Memory system with two clock lines and a memory device The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a fir... | 02/06/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7174233 | Quality/reliability system and method in multilevel manufacturing environment This is a system and method for management system. The system and method includes a raw pull indicator database which receives inputs comprising data from participant nodes. A system comprises execution logic which operates on the data from the raw pull indicator. A... | 02/06/2007 |
| 7171574 | DDR clocking A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit... | 01/30/2007 |
| 7171445 | Fixed snoop response time for source-clocked multiprocessor busses An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over fast... | 01/30/2007 |
| 7170505 | Display apparatus drive circuit having a plurality of cascade connected driver ICs To prevent a timing shift of a clock and data supplied to a driver IC. A driver 1011 includes a phase adjustment circuit 201 for receiving via input terminals a clock and data outputted from a controller 103, latching received data with t... | 01/30/2007 |
| 7167966 | Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. ... | 01/23/2007 |
| 7164998 | Method for determining programmable coefficients to replicate frequency and supply voltage correlation in an integrated circuit One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine grain delay systhesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of a... | 01/16/2007 |
| 7165185 | DDR II write data capture calibration A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the dat... | 01/16/2007 |
| 7162567 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 01/09/2007 |
| 7162382 | Apparatus and method for calibrating signals The invention is directed to a device for calibrating signals, whereby at least two signal circuits are provided for generating signals. In order to calibrate the signals, elements are provided that evaluate the signals generated by the signal circuits and, dependen... | 01/09/2007 |
| 7161402 | Programmable delay locked loop A delay lock loop (DLL) system includes a master DLL and at least one slave DLL. The master DLL comprises a master delay line, a phase detector, and a loop controller. The master delay line of the master DLL includes four quarter cycle delay lines (QCDL). The slave ... | 01/09/2007 |
| 7161400 | Phase synchronization for wide area integrated circuits A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signa... | 01/09/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7159136 | Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi... | 01/02/2007 |
| 7159067 | Information processing apparatus using index and TAG addresses for cache In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache conten... | 01/02/2007 |
| 7159138 | Method and apparatus for data transfer between at least two modules interconnected by a serial data bus Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiv... | 01/02/2007 |
| 7158592 | Method and apparatus for synchronizing data transfer The invention is a method and apparatus for ensuring synchronization for digital communication between a transmitting and a receiving device, particularly when the clock and/or frame synchronization is sourced from a different location than the transmit data. ... | 01/02/2007 |
| 7159137 | Synchronized communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 01/02/2007 |
| 7158920 | Noise checking method and apparatus and computer-readable recording medium which records a noise checking program The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire... | 01/02/2007 |
| 7155626 | Data processor including clock thinning-out circuit A data processor which may prevent data processing being executed from being analyzed based on the power consumption has been disclosed. A data processor (100) may include clock generating circuit (101), a random number generating circuit (102),... | 12/26/2006 |
| 7155627 | Memory system and data transmission method A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delay... | 12/26/2006 |
| 7152176 | Dynamic resynchronization of clocked interfaces One or more methods and systems of resynchronizing or dynamically retuning a clock signal over a high speed clocked data interface are presented. In one embodiment, the system and method utilizes first and second delay lines, a first pair of digital logic devices to... | 12/19/2006 |
