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| Number | Title | Issue Date |
| 5210858 | Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor A clocking control circuit for a computer system and method for receiving a microprocessor clock signal which drives a microprocessor and for supplying a support clock signal having a lower frequency. The support clock frequency drives support interface c... | 05/11/1993 |
| 5150313 | Parallel pulse processing and data acquisition for high speed, low error flow cytometry A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all ... | 09/22/1992 |
| 5133069 | Technique for placement of pipelining stages in multi-stage datapath elements with an automated circuit design system According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, th... | 07/21/1992 |
| 5123100 | Timing control method in a common bus system having delay and phase correcting circuits for transferring data in synchronization and time division slot among a plurality of transferring units In a common bus control method, transmission and reception buses are connected to a unit having a unit number 1. A synchronization frame head signal for time-division slots of common buses is sequentially supplied to the units in the order of the unit num... | 06/16/1992 |
| 5086500 | Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lin... | 02/04/1992 |
| 4989175 | High speed on-chip clock phase generating system A plurality of synchronized phase generators are provided in a mainframe computer of the type having unit card each of which contain a plurality of very large scale integrated (VLSI) logic chips. Each logic chip has its own on-chip phase generator which i... | 01/29/1991 |
| 4984195 | Extended bus controller An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control ... | 01/08/1991 |
| 4975593 | Microcomputer with synchronized data transfer A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal chang... | 12/04/1990 |
| 4928000 | Method and apparatus for communication for a data-storing token A data-storing token includes a microprocessor which responds to a signal generated by a token interrogator for altering its clock frequency so as to achieve synchronization between the token and interrogator operations. Additional synchronization is achi... | 05/22/1990 |
| 4916659 | Pipeline system with parallel data identification and delay of data identification signals A pipeline system which is suitable for the processing of data accompanied by data identifying signals comprises interconnected modules which process the data and which controllably transfer the data to one another. Data processing in a module introduces ... | 04/10/1990 |
| 4888684 | Multiprocessor bus protocol A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system ... | 12/19/1989 |
| 4884198 | Single cycle processor/cache interface An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor gen... | 11/28/1989 |
| 4835728 | Deterministic clock control apparatus for a data processing system A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal an... | 05/30/1989 |
| 4809221 | Timing signal generator A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherentl... | 02/28/1989 |
| 4807109 | High speed synchronous/asynchronous local bus and data transfer method A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message... | 02/21/1989 |
| 4789959 | Delay circuit for a real time clock A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.... | 12/06/1988 |
| 4785415 | Digital data buffer and variable shift register A combination FIFO buffer and programmable shift register having asynchronous input and output capabilities comprises a three stage system which synchronizes the incoming data stream with the memory input clock, buffers the incoming data stream and provid... | 11/15/1988 |
| 4593379 | Method and a device for synchronization of messages A method and device for synchronization of messages, wherein the phase of a reception clock signal is controlled in dependence on the phase of the messages received by causing the absolute value of the phase of the reception clock signal to vary by the qu... | 06/03/1986 |
| 4580243 | Circuit for duplex synchronization of asynchronous signals The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronizati... | 04/01/1986 |
| 4570219 | CMOS Circuit with reduced power dissipation and a digital data processor using the same In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first in... | 02/11/1986 |
| 4486832 | Sequential program control system To provide for uniform timing of program control cycles in which different control cycles have different cycling time, the control cycles being connected in parallel to a program control arrangement, timing elements are connected in the respective signal ... | 12/04/1984 |
| 4464584 | Microprocessor with resetting circuit arrangement In a microprocessor with a reset circuit arrangement acting in dependence upon the inception of its supply voltage, safe operation is ensured after stoppages or operating voltage interruptions, particularly in view of a delay of the internal program flow ... | 08/07/1984 |
| 4426685 | Solid state delay device A solid state delay device for delaying digital data for short periods of me. Serial digital data is converted into parallel data and input to a number of parallel memory paths. The data is shifted through the memory paths by a clock synchronized with the... | 01/17/1984 |
| 4415984 | Synchronous clock regenerator for binary serial data signals Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw... | 11/15/1983 |
| 4386401 | High speed processing restarting apparatus The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the c... | 05/31/1983 |
| 4375103 | Method and apparatus of signalling request to send clear to send delay Disclosed are a method and apparatus for exchanging information between a data terminal equipment (DTE) and data circuit terminating equipment (DCE) or controller connected to the data terminal equipment over a communications line. The specific informatio... | 02/22/1983 |
| 4347582 | Central timer unit for buffering control data in a telecommunications system In a central timer unit (CTU), incoming stochastically occurring control information, for example dial pulse data, which is to be buffered for execution after individually assigned delay times, is stored in a random access memory (RAM). Address linkage in... | 08/31/1982 |
| 4330824 | Universal arrangement for the exchange of data between the memories and the processing devices of a computer An interface for the exchange of data between memories and processing devices of a computer, which interface does not depend on any particular technology of the processing and memory units and which is readily adaptable to units having different timing fo... | 05/18/1982 |
| 4295220 | Clock check circuits using delayed signals In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pul... | 10/13/1981 |
| 4079456 | Output buffer synchronizing circuit having selectively variable delay means Output buffer synchronizing circuit having selectively variable delay means to compensate for different output delays of a processor when the latter operates in different modes. A buffer clock is not only synchronized with the processor clock but also swi... | 03/14/1978 |
| 4021784 | Clock synchronization system In a fail soft synchronization clock system having a plurality of central processing units and a plurality of input-output units operably connected to one or more remotely located volatile cache memories there is provided a free-running, non-synchronized ... | 05/03/1977 |
