Class 713/401 - Using delay

Subclass of Class 713 - Electrical computers and digital processing systems: support
Definition: Subject matter wherein the clock or timing signals, timing
No. of patents: 1032
Last issue date: 05/15/2012

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Number	Title	Issue Date
7627772	Fast data access mode in a memory device A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequenc...	12/01/2009
RE40990	Data transmission across asynchronous time domains using phase-shifted data packet A method and apparatus is provided for transmitting multi-bit data across asynchronous time domains. In one embodiment, the apparatus includes a first delay circuit to generate a selector signal based upon an input reference signal of a first time domain, a second d...	11/17/2009
7610503	Methods for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th...	10/27/2009
7610502	Computer systems having apparatus for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th...	10/27/2009
7594133	Method and apparatus for determining a deviation between clock pulse devices The invention relates to a method for synchronizing clock pulse devices. According to this method, an emission unit emits at least one narrow-band distant signal; clock pulse devices of receiving units are pre-synchronized by coupling the same to the source of one s...	09/22/2009
7590879	Clock edge de-skew Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further em...	09/15/2009
7581131	Method and system for balancing clock trees in a multi-voltage synchronous digital environment A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain. Similarly, a second so...	08/25/2009
7565563	Non-volatile memory arrangement and method in a multiprocessor device This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. T...	07/21/2009
7555667	Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source syn...	06/30/2009
7543172	Strobe masking in a signaling system having multiple clock domains Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components o...	06/02/2009
7526664	Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi...	04/28/2009
7506193	Systems and methods for overcoming part to part skew in a substrate-mounted circuit Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable delay buffer such that compensation for a skewed signal may be continu...	03/17/2009
7500129	Adaptive communication interface Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports...	03/03/2009
7493509	Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systems A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair s...	02/17/2009
7490257	Clock distributor for use in semiconductor logics for generating clock signals when enabled and a method therefor A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a...	02/10/2009
7487377	Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operate...	02/03/2009
7478256	Coordinating data synchronous triggers on multiple devices System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices sha...	01/13/2009
7472304	Double data rate system An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs ...	12/30/2008
7467317	Memory system and data transmission method A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delay...	12/16/2008
7457978	Adjustable byte lane offset for memory module to reduce skew Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits...	11/25/2008
7444565	Re-programmable COMSEC module A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output fro...	10/28/2008
7443940	Alignment mode selection mechanism for elastic interface Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock ed...	10/28/2008
7444531	Methods and devices for treating and processing data A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the...	10/28/2008
7444533	Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by ...	10/28/2008
7444535	Method and related apparatus for adjusting timing of memory signals A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger...	10/28/2008
7440531	Dynamic recalibration mechanism for elastic interface A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points with...	10/21/2008
7437580	Dynamic voltage scaling system Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the...	10/14/2008
7434078	Synchronization with hardware utilizing software clock slaving via a clock A sample rate converter (SRC) is used to slave hardware devices to a master hardware device. A clock manager registers the time at each clock of each device, communicates with memory that stores the clock times, and reports correlations between each clock time and t...	10/07/2008
7430680	System and method to align clock signals A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers...	09/30/2008
7424634	System and method for reducing jitter of signals coupled through adjacent signal lines A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects each of the transitions of the digital signals. The mode detector determines respective propagation time...	09/09/2008
7424635	System and method for power saving delay locked loop control by selectively locking delay interval The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will no...	09/09/2008
7421606	DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x ...	09/02/2008
7421607	Method and apparatus for providing symmetrical output data for a double data rate DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, arr...	09/02/2008
7418616	System and method for improved synchronous data access A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are ...	08/26/2008
7418617	Apparatus for adjusting timing of memory signals An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit c...	08/26/2008
7414900	Method and system for reading data from a memory Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route...	08/19/2008
7412616	Semiconductor integrated circuit A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM....	08/12/2008
7412618	Combined alignment scrambler function for elastic interface An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambl...	08/12/2008
7409568	Power supply voltage droop compensated clock modulation for microprocessors A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected. ...	08/05/2008
7401245	Count calibration for synchronous data transfer between clock domains Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The s...	07/15/2008

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Class 713/401 - Using delay