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| Number | Title | Issue Date |
| 7121455 | Systems and methods for electronic postmarking including ancillary data An embodiment of the invention provides a method for performing electronic postmarking of data, including ancillary data is provided. The method includes receiving data from a sender. The method further includes selecting ancillary data. The method further includes ... | 10/17/2006 |
| 7123064 | Digital phase shift circuits Techniques are presented for creating a second clock signal by using a first clock signal. For instance, an output is determined that corresponds to a phase relationship between the first and second clock signals. A value, corresponding to a given one of a plurality... | 10/17/2006 |
| 7124263 | Memory controller, semiconductor integrated circuit, and method for controlling a memory A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enabl... | 10/17/2006 |
| 7120723 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 10/10/2006 |
| 7120743 | Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to t... | 10/10/2006 |
| 7119593 | Delayed signal generation circuits and methods Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked ... | 10/10/2006 |
| 7120727 | Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr... | 10/10/2006 |
| 7120815 | Clock circuitry on plural integrated circuits Clock circuitry supplies synchronized clock waves to loads on plural integrated circuit chips. The clock circuitry couples the synchronized clock waves to regions of the chips. There is a first clock wave route in a first direction from a first chip to a second chip... | 10/10/2006 |
| 7120814 | System and method for aligning signals in multiple clock systems A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement ... | 10/10/2006 |
| 7120774 | Efficient management of memory access requests from a video data stream A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the reque... | 10/10/2006 |
| 7120813 | Method and apparatus for clock synthesis using universal serial bus downstream received signals In one form of the invention, a method for generating a local clock signal responsive to signals on a Universal Serial Bus (“USB”) includes generating a frequency-bearing clock signal by a free running oscillator on an integrated circuitry chip of a device coupl... | 10/10/2006 |
| 7117436 | Generating a Web page by replacing identifiers in a preconstructed Web page A system and method for dynamically generating Web content using a parse tree is described. A template describing a dynamically generated Web page is built. The template includes a script written in a tag-delimited page description language. One or more markers incl... | 10/03/2006 |
| 7117378 | Adaptive voltage scaling digital processing component and method of operating the same There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum... | 10/03/2006 |
| 7117316 | Memory hub and access method having internal row caching A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the mem... | 10/03/2006 |
| 7117382 | Variably controlled delay line for read data capture timing window Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input stro... | 10/03/2006 |
| 7116602 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/03/2006 |
| 7116961 | Image rejection quadratic filter An image rejection quadratic filter is tunable to filter image frequencies over a wide band. In one embodiment, the image rejection filter includes in-phase and quadrature phase mixers. The image rejection has a fractional transfer function. The image rejection filt... | 10/03/2006 |
| 7117292 | Apparatus and method to switch a FIFO between strobe sources A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latche... | 10/03/2006 |
| 7117419 | Reliable communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 10/03/2006 |
| 7111184 | System and method for deterministic communication across clock domains A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable off... | 09/19/2006 |
| 7111185 | Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at va... | 09/19/2006 |
| 7110446 | Method and apparatus for reducing effect of jitter Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically p... | 09/19/2006 |
| 7110461 | Technique to enlarge data eyes in wireline communication systems A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit include... | 09/19/2006 |
| 7110932 | Method and circuit arrangement for regulating the operating voltage of a digital circuit A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by ... | 09/19/2006 |
| 7107415 | Posted write buffers and methods of posting write requests in memory modules A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are al... | 09/12/2006 |
| 7107424 | Memory read strobe pulse optimization training system A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a co... | 09/12/2006 |
| 7107474 | Data transfer unit and method A data transfer unit (13) is provided for use in a clock swapping system which controls data transfer with a data transmission permit signal (rwo) and data reception permit signal (rro). The data transfer unit (13) includes a data latch (21) whi... | 09/12/2006 |
| 7107475 | Digital delay locked loop with extended phase capture range A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updat... | 09/12/2006 |
| 7106611 | Wavelength division multiplexed memory module, memory system and method A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the... | 09/12/2006 |
| 7107477 | Programmable logic devices with skewed clocking signals A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic dev... | 09/12/2006 |
| 7103815 | Testing of integrated circuit devices An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The... | 09/05/2006 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 09/05/2006 |
| 7102450 | Method and apparatus for providing clock signals at different locations with minimal clock skew A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desir... | 09/05/2006 |
| 7103790 | Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double dat... | 09/05/2006 |
| 7103758 | Microcontroller performing safe recovery from standby mode A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcont... | 09/05/2006 |
| 7103694 | Method and apparatus implementing a tuned stub SCSI topology In one aspect, the invention is a tuned stub, SCSI topology comprising a SCSI bus, a breakout node on the SCSI bus, an external SCSI connector on the SCSI bus at a first point defined by a first propagation delay; an internal SCSI connector on the SCSI bus at a seco... | 09/05/2006 |
| 7103126 | Method and circuit for adjusting the timing of output data based on the current and future states of the output data A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a ph... | 09/05/2006 |
| 7102907 | Wavelength division multiplexed memory module, memory system and method A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the... | 09/05/2006 |
| 7102465 | Frequency discrete LC filter bank An inductive (“L”)-capacitive (“C”) filter bank has application for use in a television receiver. The LC filter includes inductors configured in at least one inductive (“L”) bank, and capacitors configured in at least one capacitive (“C”) bank. The i... | 09/05/2006 |
| 7103791 | Interleaved delay line for phase locked and delay locked loops An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the ... | 09/05/2006 |
