Class 713/401 - Using delay

Subclass of Class 713 - Electrical computers and digital processing systems: support
Definition: Subject matter wherein the clock or timing signals, timing
No. of patents: 1024
Last issue date: 12/20/2011

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8082463	Dynamic programmable delay selection circuit and method A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert ...	12/20/2011
8082462	Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The ratio...	12/20/2011
8065550	Digital delay locked loop circuit using mode register set A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator ...	11/22/2011
8065551	Adjustable byte lane offset for memory module to reduce skew Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits...	11/22/2011
8060770	Method and system for clock skew reduction in clock trees A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of f...	11/15/2011
8037336	Spread spectrum clock generation The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flat...	10/11/2011
8020022	Delay time control of memory controller A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the p...	09/13/2011
7987381	Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the pe...	07/26/2011
7945801	Semiconductor integrated circuit A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM....	05/17/2011
7945800	Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points ...	05/17/2011
7937604	Method for generating a skew schedule for a clock distribution network containing gating elements A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals t...	05/03/2011
7913101	Method and apparatus for treating a signal A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion ...	03/22/2011
7890786	Memory controller and signal synchronizing method thereof A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer an...	02/15/2011
7886176	DDR memory system for measuring a clock signal by identifying a delay value corresponding to a changed logic state during clock signal transitions Circuits for measuring a clock signal include a variable digital delay line that is configured to delay the clock signal by variable amounts in response to variable values of a digital control word that are applied thereto, to produce a variably delayed clock signal...	02/08/2011
7873857	Multi-component module fly-by output alignment arrangement and method A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount...	01/18/2011
7861105	Clock data recovery (CDR) system using interpolator and timing loop module The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay res...	12/28/2010
7849346	Dynamic programmable delay selection circuit and method A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert ...	12/07/2010
7849345	DDR control A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system cloc...	12/07/2010
7827429	Fault tolerant computer A fault tolerant computer comprises a first unit, a second unit, a delay buffer and a delay time setting unit. The first unit executes a computer program in response to an input signal. The second unit executes the computer program in the same execution environment ...	11/02/2010
7823001	Latency adjustment between integrated circuit chips In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link be...	10/26/2010
7818601	Method and apparatus for data transfer A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one emb...	10/19/2010
7814362	System and method for power saving delay locked loop control The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will no...	10/12/2010
7809972	Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The sec...	10/05/2010
7783911	Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip ...	08/24/2010
7752477	Signal processor and method for processing a signal A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the reference clock. A frequency controller is configured to sample a count valu...	07/06/2010
7721135	Method of timing calibration using slower data rate pattern An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the d...	05/18/2010
7716511	Dynamic timing adjustment in a circuit device A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an out...	05/11/2010
7707448	Deterministic test strand unparking A circuit for deterministic unparking of a strand of a microprocessor having multiple clock domains is described. The circuit includes a first flip-flop and a second flip-flop. Each flip-flop has a data input connected to receive a respective unpark signal, a clock ...	04/27/2010
7698589	Memory controller and device with data strobe calibration A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is c...	04/13/2010
7657771	Method and apparatus for reducing latency associated with read operations in a memory system Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in acco...	02/02/2010
7644296	Programmable logic device integrated circuits with configurable dynamic phase alignment circuitry Programmable logic device integrated circuits are provided that have configurable receivers with dynamic phase alignment capabilities. In situations in which receivers require dynamic phase alignment circuitry, programmable logic elements can be configured to implem...	01/05/2010
7640448	Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi...	12/29/2009
7627772	Fast data access mode in a memory device A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequenc...	12/01/2009
RE40990	Data transmission across asynchronous time domains using phase-shifted data packet A method and apparatus is provided for transmitting multi-bit data across asynchronous time domains. In one embodiment, the apparatus includes a first delay circuit to generate a selector signal based upon an input reference signal of a first time domain, a second d...	11/17/2009
7610502	Computer systems having apparatus for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th...	10/27/2009
7610503	Methods for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th...	10/27/2009
7594133	Method and apparatus for determining a deviation between clock pulse devices The invention relates to a method for synchronizing clock pulse devices. According to this method, an emission unit emits at least one narrow-band distant signal; clock pulse devices of receiving units are pre-synchronized by coupling the same to the source of one s...	09/22/2009
7590879	Clock edge de-skew Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further em...	09/15/2009
7581131	Method and system for balancing clock trees in a multi-voltage synchronous digital environment A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain. Similarly, a second so...	08/25/2009
7565563	Non-volatile memory arrangement and method in a multiprocessor device This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. T...	07/21/2009

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 713/401 - Using delay