Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8190942 | Method and system for distributing a global timebase within a system-on-chip having multiple clock domains A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code over a global timebase bus. A global timebase generator includes a bina... | 05/29/2012 |
| 8185768 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 05/22/2012 |
| 8185769 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 05/22/2012 |
| 8176351 | Sampling mechanism for data acquisition counters One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement ... | 05/08/2012 |
| 8166333 | Network signal processing apparatus A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing... | 04/24/2012 |
| 8151131 | Signal synchronization method and signal synchronization circuit There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in synchronization with a second clock signal with a different cycle fr... | 04/03/2012 |
| 8140882 | Serial bus clock frequency calibration system and method thereof A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resol... | 03/20/2012 |
| 8140881 | Circuitry and method for detection of network node aging in communication networks The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and... | 03/20/2012 |
| 8135975 | Software programmable timing architecture A first output count is compared with first and second stored count values for generating an output event at a first node if the first Output count corresponds to the first or second stored count values. ... | 03/13/2012 |
| 8132036 | Reducing latency in data transfer between asynchronous clock domains A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are... | 03/06/2012 |
| 8127169 | Semiconductor memory device and method for generating internal control signal A semiconductor memory device includes: a command input unit configured to receive a plurality of external commands in synchronization with a rising edge of an internal clock to generate a plurality of pre-control signals; an output control signal generating unit co... | 02/28/2012 |
| 8127170 | Method and apparatus for audio receiver clock synchronization An audio receiver's output clock is synchronized based on a number of input and output audio samples measured over a predetermined sample period. In one embodiment, a sample difference may be determined by subtracting the measured number of input audio samples from ... | 02/28/2012 |
| 8122274 | Method, system and computer program product for certifying a timestamp of a data processing system The disclosed embodiments present a system, method, and computer program product for certifying a timestamp generated by a data processing system. In some embodiments, the method includes receiving a request to certify a timestamp generated by a trusted data process... | 02/21/2012 |
| 8117481 | Apparatus and method for processing wirelessly communicated information within an electronic device An electronic device (12) for processing information wirelessly received from another electronic device (14) or to be wirelessly sent to the another electronic device (14) may include a first processor (20) that controls only wireless com... | 02/14/2012 |
| 8108707 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 01/31/2012 |
| 8108706 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 01/31/2012 |
| 8103896 | Method and system for I2C clock generation I2C clock generators are implemented using a variety of methods. Using one such method, a method is implemented using logic circuitry arranged in a state machine to control the clock signal (110) on the I2C bus. A first state (202... | 01/24/2012 |
| 8099618 | Methods and devices for treating and processing data A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the... | 01/17/2012 |
| 8090972 | Method and system for registering events in wind turbines of a wind power system The invention relates to a method of registering events in a wind power system comprising at least two data processors, wherein the data processors of said wind power system are mutually time synchronized, wherein events are registered in said at least two data proc... | 01/03/2012 |
| 8090971 | Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation t... | 01/03/2012 |
| 8074095 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 12/06/2011 |
| 8069363 | Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs d... | 11/29/2011 |
| 8065549 | Scan-based integrated circuit having clock frequency divider An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually differe... | 11/22/2011 |
| 8055930 | Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency gr... | 11/08/2011 |
| 8055929 | Method and apparatus for maintaining time in a computer system A computer system is arranged with a circular buffer that includes a piecewise linear map from a high-resolution counter arranged to maintain International Atomic Time. The piecewise linear map includes a current leg that is currently being used and also a future le... | 11/08/2011 |
| 8046620 | Interactive device with time synchronization capability An interactive device having time synchronization capability is provided. In one embodiment of the present invention, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements... | 10/25/2011 |
| 8041978 | Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main dat... | 10/18/2011 |
| 8041979 | Method and a system for synchronising respective state transitions in a group of devices A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least ... | 10/18/2011 |
| 8037335 | Apparatus and method for synchronizing a channel card in a mobile communication system An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sen... | 10/11/2011 |
| 8001409 | Synchronization device and methods thereof A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain... | 08/16/2011 |
| 7996699 | System and method for synchronizing multiple media devices Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end co... | 08/09/2011 |
| 7996700 | Media data synchronization in a wireless network A method of keeping global time in a wireless network, the method includes reading a Time Synchronization Function (TSF) to provide an initial time base. An interconnected clock control circuit is employed to read the TSF time from the circuitry used to read the TSF... | 08/09/2011 |
| 7984319 | Memory bus shared system The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared ... | 07/19/2011 |
| 7979730 | Method and device for synchronizing cycle time of a plurality of TTCAN buses based on determined global time deviations and a corresponding bus system A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, there being cycle times of the basic cycles in the TTCAN buses, a global time being determined in each TTCAN bus and the deviations of the global times of t... | 07/12/2011 |
| 7949890 | Method and system for precise synchronization of audio and video streams during a distributed communication session with multiple participants Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve synchronization, methods of introducing buffering delays to create hand... | 05/24/2011 |
| 7945799 | HVAC synchronization Systems and methods are described for synchronizing an HVAC control system. A method, includes: a synchronization sequence including: reading a base time from an internal clock at a first time and saving the base time; measuring an elapsed time interval, from the fi... | 05/17/2011 |
| 7941684 | Synchronization of processor time stamp counters to master counter In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller co... | 05/10/2011 |
| 7934112 | Rate verification of an incoming serial alignment sequence A technique for rate verification of an incoming serial alignment sequence includes receiving an incoming serial stream. A determination is then made as to whether an align sequence is recognized in the incoming serial stream. When an align sequence is recognized, a... | 04/26/2011 |
| 7917793 | Apparatus providing locally adaptive retiming pipeline with swing structure The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor using a low voltage. Thus, synchronization problems in a chip under diffe... | 03/29/2011 |
| 7900079 | Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands ... | 03/01/2011 |
