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| Number | Title | Issue Date |
| 7321973 | System for controlling power to a system part using a control unit and wherein the power to the control unit is controlled using a power controller An electronic device includes a system part having a plurality of electronic components; a system power supply outputting a system operating power by transforming electrical power supplied from the battery pack into the system operating power to operate the system p... | 01/22/2008 |
| 7320077 | Power supply controlling apparatus of a device connected to a serial bus The present invention relates to an apparatus and method of a Universal Serial Bus (USB) device to control power supply for USB devices coupled to a host through a USB and to control power supply for the coupled USB devices based on whether the USB devices are opera... | 01/15/2008 |
| 7320078 | Controlling delivery of power and network communications to a set of devices An improved assembly (e.g., an integrated power cycler and terminal server) controls power and communications to a set of devices. The assembly includes a network port configured to connect to a network, a set of device ports configured to connect to the set of devi... | 01/15/2008 |
| 7320064 | Reconfigurable computing architecture for space applications A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port commu... | 01/15/2008 |
| 7318146 | Peripheral device with hardware linked list A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a qu... | 01/08/2008 |
| 7318170 | Protection of non-volatile memory component against data corruption due to physical shock This invention provides a method to operate a terminal (100), as well as a terminal that operates in accordance with the method. The method includes, in response to initiating a data write operation with a non-volatile memory device (132), activating a... | 01/08/2008 |
| 7315953 | Apparatus and related method of coordinating north bridge and south bridge for processing bus master requests of peripheral devices for controlling a central processing unit to operate in a power-saving state A connected indicator wire of open-drained configuration is set between a north bridge and a south bridge. When either the south or north bridge is handling a bus master request, a bus master indicator (BMI) signal is asserted to the connected indicator wire. With o... | 01/01/2008 |
| 7313710 | High quality and high performance three-dimensional graphics architecture for portable handheld devices A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be... | 12/25/2007 |
| 7313712 | Link power saving state Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enable... | 12/25/2007 |
| 7313709 | Instruction set with thermal opcode for high-performance microprocessor, microprocessor, and method therefor A method (and system) of managing heat in an electrical circuit, includes using a thermal instruction appended to an instruction to be processed to determine a heat load associated with the instruction. ... | 12/25/2007 |
| 7313713 | Sequential/combinational logic transistor segregation for standby power and performance optimization A method and apparatus for powering digital logic circuits that provides low power consumption while maintaining high performance. The circuit is divided into logic elements necessary for maintaining the state of the circuit and those that are not. The state-maintai... | 12/25/2007 |
| 7313707 | Systems and methods for configuring ports Systems, methodologies, media and other embodiments associated with configuring a port are described. One exemplary system embodiment includes a computing system that includes a port configured to operably connect an external device to the computing system. The exam... | 12/25/2007 |
| 7313708 | Interlocked plug and play with power management for operating systems The present invention provides a unified layer for Plug and Play (PnP) components and power management components while relieving device drivers from system-level complexities associated with implementing PnP and/or power management functionality. The layer operates... | 12/25/2007 |
| 7310737 | Cooling system for computer systems A cooling system for cooling computer systems detects heat dissipated by the computer systems. If the heat dissipated by the computer systems exceeds a threshold, at least one component of the computer systems is placed in a lower-power state to reduce heat dissipat... | 12/18/2007 |
| 7310740 | System and method for a configurable portable information handling system cover switch delay Power down to a reduced power state, such as a standby or off state, of an information handling system is delayed by a user-configured time after detection of closing of the cover of the information handling system. In one embodiment, a cover delay module associated... | 12/18/2007 |
| 7308591 | Power management of multi-processor servers A method and system are provided for dynamically managing delivery of power to partitionable elements in a computer system while supporting terms of a Service Level Agreement (SLA). Parameters of the SLA are gathered in conjunction with the topology of the computer ... | 12/11/2007 |
| 7308590 | Automatic dynamic processor operating voltage control A technique to adjust a processor's operating voltage dynamically while preventing a user from placing the processor into a harmful operating voltage state in relation to the core/bus frequency ratio of the processor. More particularly, embodiments of the invention ... | 12/11/2007 |
| 7304584 | Wireless input device with low voltage mandatory alert function The present invention relates to a wireless input device with a low voltage mandatory alert function, including: a battery for supplying power for the wireless input device; a microcontroller for handling the input signals of the wireless input device. The present i... | 12/04/2007 |
| 7305568 | Backup system for multi-source audio apparatus In a backup system 310, 340, 350, or 360, a controller 300 controls operation of a multi-source audio apparatus MMSA. An operation status holder 310 holds operation status information Dbk of the multi-source audio apparatus MMSA. A non-vo... | 12/04/2007 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7305567 | Decoupled architecture for data ciphering operations In one embodiment, an apparatus comprises a microcontroller unit to store instructions into an execution queue. The apparatus also comprises an execution queue unit to generate a widely decoded functional execution instruction based on at least one instruction store... | 12/04/2007 |
| 7302600 | Power supply detection method, apparatus, and system Circuits in a processor may provide an indication that power supplies are ready when waking from a reduced power state. The processor may include timers to measure a period of time, and may utilize voltage detectors to detect the voltages on the power supplies. A co... | 11/27/2007 |
| 7302595 | Method and apparatus for dynamic power management in a processor system A dynamic power management system includes an operating system (OS) that causes a processor to operate in one of multiple run states that have different performance and/or power dissipation levels. The OS selects the run state in response to processor information (e... | 11/27/2007 |
| 7302652 | Leakage control in integrated circuits Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduc... | 11/27/2007 |
| 7299370 | Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodi... | 11/20/2007 |
| 7296171 | Selecting a power state based on predefined parameters An algorithm automatically selects a power state based on device configuration parameters. The selected power state may then be returned and/or automatically implemented in a shutdown of the device. The parameters can include whether the device supports a system bat... | 11/13/2007 |
| 7296164 | Power management scheme for external batteries In a method and system for managing power provided to a load, a power supply system includes a first power peripheral operable to receive and convert a first type of power to a second type of power. Also included in the power supply system is a second power peripher... | 11/13/2007 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
| 7295197 | Flat-panel display apparatus and its control method A display apparatus includes a display panel having a plurality of display elements, and a display controller for controlling the display panel in a normal display mode, a first power saving mode, a second power saving mode and a third power saving mode. A mode tran... | 11/13/2007 |
| 7296112 | High bandwidth memory management using multi-bank DRAM devices The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are sto... | 11/13/2007 |
| 7296107 | System and method for detection of an accessory device connection status Embodiments of this invention provide for a portable computer that determines whether an accessory device is actively connected to it. In one embodiment, the portable computer may include a signal line accessible through an output of the portable computing device. T... | 11/13/2007 |
| 7296129 | System, method and storage medium for providing a serialized memory interface with a bus repeater A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies v... | 11/13/2007 |
| 7293184 | Programmatic binding for power management events involving execution of instructions in a first programming system with a first interface and a second programming system with a second interface A plurality of instructions corresponding to a power management event are received. An instruction of the plurality of instructions is executed in a first programming system with a first interface, in response to determining that the instruction is in accordance wit... | 11/06/2007 |
| 7293182 | Methods and apparatus for powering a data communications port A data communications device includes a supervisory circuit, a power supply, and a power circuit. The power circuit includes a data communications port, a power supply connection coupled to the power supply, and a power controller coupled to the data communications ... | 11/06/2007 |
| 7293188 | Low voltage detection system A low voltage detection (LVD) system for a logic device includes a first LVD circuit (110) to provide an indicator when a supply pin voltage (109) falls below a first voltage level, and a second LVD circuit (116) to provide an interrupt (118 | 11/06/2007 |
| 7293113 | Data communication system with hardware protocol parser and method therefor A communication processor comprises a data link layer parser circuit (310) and a plurality of network layer parser circuits (322, 326). The data link layer parser circuit (310) receives a data link layer frame, and removes a data link layer head... | 11/06/2007 |
| 7293187 | Image sensing apparatus and power managing method If supply of power from a main power source is insufficient but power being supplied from a communication interface (such as a USB interface) is sufficient, an image sensing apparatus (such as a digital video camera or digital camera) supplies power from the communi... | 11/06/2007 |
| 7290089 | Executing cache instructions in an increased latency mode For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle a... | 10/30/2007 |
| 7290171 | Device driver and device A device connected to a bus and a device driver for controlling the device, capable of preventing the device from falling into a forced use suspension (disable) state. Prior to notice of power consumption by a USB device connected to the bus(USB), the device driver ... | 10/30/2007 |
| 7290157 | Configurable processor with main controller to increase activity of at least one of a plurality of processing units having local program counters A processor comprises a main controller (CTR11) and a plurality of processing units (1–9). Each processing unit (1–9) has a local controller (CTR1–CTR9) and at least one functional unit (FU1–FU9) controllable ... | 10/30/2007 |
