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| Number | Title | Issue Date |
| 8001384 | Authentication system, authentication method, attesting device, verification device, their programs, and recording medium A verification device stores verification information and first random information in a storage. The verification information depends upon contents of comparative information, and not upon an information volume of the comparative information. The verification device... | 08/16/2011 |
| 7904719 | Extending the range of computational fields of integers An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field,... | 03/08/2011 |
| 7802098 | Cryptography method and smart cards microcircuit Method of cryptography in a smart card comprising a central processing unit, said method implementing precomputation operations, characterized in that said precomputation operations are performed by the smart card and in that the precomputation operations are carrie... | 09/21/2010 |
| 7603558 | Montgomery transform device, arithmetic device, IC card, encryption device, decryption device and program According to an aspect of the invention, Montgomery arithmetic can be achieved while omitting division in an input stage. That is, the aspect of the invention is configured to obtain a Montgomery transform result m′ (=mR mod p) of n-bit from an input m of 2n-bit w... | 10/13/2009 |
| 7437757 | Token for use in online electronic transactions An online transaction system configured to implement authentication methods that allow for strong multi-factor authentication in online environments. The authentication methods can be combined with strong security methods to further ensure that the authentication pr... | 10/14/2008 |
| 7409558 | Low-latency data decryption interface Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined ... | 08/05/2008 |
| 7386122 | Method for proving the authenticity or integrity of a message by means of a public exponent equal to the power of two Proof is established by means of the following parameters: m pairs of private values Q1 and public values G1 m>1, a public module n made of the product of f first factors pj, f>2, a public exponent v, linked to each other by relation... | 06/10/2008 |
| 7364083 | IC card with built-in coprocessor for auxiliary arithmetic, and control method thereof An IC card according to the present invention comprises, a built-in coprocessor for an auxiliary arithmetic in addition to a main arithmetic processing unit, an interval timer for outputting an interrupt request signal upon lapse of a set time shorter than the frame... | 04/29/2008 |
| 7320015 | Circuit and method for performing multiple modulo mathematic operations A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathe... | 01/15/2008 |
| 7313701 | Robust efficient distributed RSA-key generation The invention provides for robust efficient distributed generation of RSA keys. An efficient protocol is one which is independent of the primality test “circuit size”, while a robust protocol allows correct completion even in the presence of a minority of arbitr... | 12/25/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7266197 | Method, system, device for proving the authenticity of an entity and/or the integrity and/or the authenticity of a message using specific prime factors The proof is provided by means of the following parameters: a public module n formed by the product of f prime factors pi, f>2; a public superscript v; m base numbers gi, m>1. The base numbers gi are such that the two equations: x | 09/04/2007 |
| 7263191 | Method and apparatus for encrypting data A method for encrypting data comprising dividing a first data set into a second data set and a third data set; deriving a first value using the second data set as an input into a polynomial equation; deriving a second value using the third data set as an input into ... | 08/28/2007 |
| 7257843 | Command processing system by a management agent In a system where a management application sends commands to a remotely-located agent over a network, the agent maintains a security specification table defining the security level for each combination of the cipher and authentication algorithms of the communication... | 08/14/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7240204 | Scalable and unified multiplication methods and apparatus Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The pr... | 07/03/2007 |
| 7236593 | Apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multi... | 06/26/2007 |
| 7228436 | Semiconductor integrated circuit device, program delivery method, and program delivery system When an encrypted program and a decryption program are inputted to a first memory, a semiconductor integrated circuit device causes a bus port to disable access from the outside and enables access to the first memory and to a second memory, thereby transferring the ... | 06/05/2007 |
| 7194088 | Method and system for a full-adder post processor for modulo arithmetic A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction i... | 03/20/2007 |
| 7191333 | Method and apparatus for calculating a multiplicative inverse of an element of a prime field Techniques for implementing a digital signature algorithm in electronic computer hardware include computing the multiplicative inverse of a particular integer modulo a prime modulus by computing a first quantity modulo the prime modulus. The first quantity substanti... | 03/13/2007 |
| 7187770 | Method and apparatus for accelerating preliminary operations for cryptographic processing A method and apparatus for cryptographic data processing, includes determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is greater than the first number of binary ... | 03/06/2007 |
| 7181602 | Method for exchanging at least one secret initial value between a processing station and a chip card The invention relates to a method for exchanging at least one secret initial value between a processing station and a chip card, in an initializing step for the chip card. In the initialization of chip cards in known methods an initial value, e.g. a key, is t... | 02/20/2007 |
| 7174016 | Modular exponentiation algorithm in an electronic component using a public key encryption algorithm The present invention concerns an anti-SPA modular exponentiation algorithm in an electronic component using a public key ciphering algorithm. A pair of registers and an indicator are used to provide symmetrical processing of bits in the algorithm, so that the value... | 02/06/2007 |
| 7167559 | Information security device, exponentiation device, modular exponentiation device, and elliptic curve exponentiation device In an exponentiation device, a relatively large table is generated outside of a coprocessor so as to enable high-speed exponentiation to be performed using the small window method. The selection of data from the table and transfer of data to the coprocessor are cond... | 01/23/2007 |
| 7136484 | Cryptosystems using commuting pairs in a monoid Apparati, methods, and computer readable media for enabling two parties (1,2) to exchange encrypted messages, exchange symmetric cryptographic keys, and perform functions of public key cryptography. First and second key exchange algorithms use commuting pairs... | 11/14/2006 |
| 7123717 | Countermeasure method in an electronic component which uses an RSA-type public key cryptographic algorithm A countermeasure method in an electronic component which uses an RSA-type public key cryptographic algorithm. A first countermeasure method uses a random calculation for each new execution of the decryption algorithm with CRT. The calculations are made modulo p*r an... | 10/17/2006 |
| 7120763 | Method, array and set of several arrays for protecting several programs and/or files from unauthorized access by a process An area and a process file are assigned to each program to be protected. The process or processes that may run in the corresponding area is or are stored in a process file. When the program is running, a process attempting to access the program is checked to confirm... | 10/10/2006 |
| 7113593 | Recursive cryptoaccelerator and recursive VHDL design of logic circuits A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are recursively reduced to a combination of products and squares reduced... | 09/26/2006 |
| 7111166 | Extending the range of computational fields of integers An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field,... | 09/19/2006 |
| 7080262 | Key compression Described herein is one or more implementations for compressing one or more keys. ... | 07/18/2006 |
| 7073069 | Apparatus and method for a programmable security processor A digital logic circuit comprises a programmable logic device and a programmable security circuit. The programmable security circuit stores a set of authorized configuration security keys. The programmable security circuit compares the authorized configuration secur... | 07/04/2006 |
| 7058787 | Method and circuit for generating memory addresses for a memory buffer A method for generating sequences of memory addresses for a memory buffer having N*M locations includes making a first address and a last address of every sequence respectively equal to 0 and to N*M−1, assigning a first sequence of addresses, and each address but ... | 06/06/2006 |
| 7055033 | Integrated circuit devices with steganographic authentication and steganographic authentication methods Various embodiments pertain to an integrated circuit (IC) device, such as smart cards, electronic wallets, PC cards, and the like, and various methods for steganographically authenticating identities and authorizing transactions based on the authenticated identities... | 05/30/2006 |
| 7031995 | Method and device for modulo calculation In a data processing method, a remainder R that is produced during the division of an integer A by a prescribed integer B is calculated recursively. For this purpose, a data symbol word representing the integer A is decomposed into K data symbol part-words W0 | 04/18/2006 |
| 7027597 | Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7027598 | Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7016927 | Method and apparatus for modular multiplication In a method for modular multiplication of a multiplicand by a multiplier using a modulus, l multiplication shift values are initially determined by means of a multiplication-lookahead method while taking into account l blocks of consecutive digits of the multiplier.... | 03/21/2006 |
| 7016929 | Method and device for calculating a result of an exponentiation For calculating the result of an exponentiation Bd, B being a base and d being an exponent which can be described by a binary number from a plurality of bits, a first auxiliary quantity X is at first initialized to a value of 1. Then a second auxiliary qu... | 03/21/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
