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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 8161266 | Replicating opcode to other lanes and modifying argument register to others in vector portion for parallel operation An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iteration... | 04/17/2012 |
| 8010917 | Method and system for implementing efficient locking to facilitate parallel processing of IC designs Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism a... | 08/30/2011 |
| 7660967 | Result data forwarding in parallel vector data processor based on scalar operation issue order A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to m... | 02/09/2010 |
| 7620795 | Controller for a processor having internal memory Apparatus and method for a microcontroller are described. The microcontroller includes a microprocessor having storage and bussing for accessing the storage. A portion of the bussing is coupled to hardwired operation codes, and a portion of the storage is for storin... | 11/17/2009 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7313788 | Vectorization in a SIMdD DSP architecture A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture... | 12/25/2007 |
| 7305676 | Communication device configured for real time processing of user data to be transmitted A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned ... | 12/04/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7260217 | Speculative execution for data ciphering operations In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, where... | 08/21/2007 |
| 7237086 | Configuring a management module through a graphical user interface for use in a computer system A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based ... | 06/26/2007 |
| 7206920 | Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to th... | 04/17/2007 |
| 7196708 | Parallel vector processing A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vect... | 03/27/2007 |
| 7191312 | Configurable interconnection of multiple different type functional units array including delay type for different instruction processing An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input ... | 03/13/2007 |
| 7185176 | Processor executing SIMD instructions A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of ... | 02/27/2007 |
| 7146486 | SIMD processor with scalar arithmetic logic units A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality ... | 12/05/2006 |
| 7130985 | Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous reg... | 10/31/2006 |
| 7117277 | Flexibility of design of a bus interconnect block for a data processing apparatus A method and design tool are provided for modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block. The bus interconnect block provides a plurality of conn... | 10/03/2006 |
| 7075539 | Apparatus and method for processing dual format floating-point data in a graphics processing system A computing system has a graphics processor, a graphics memory, main memory, a bridge, and a central processing unit configured to process floating-point data of a first fixed size. An interconnect grid includes communication paths to link the graphics processor, th... | 07/11/2006 |
| 7062633 | Conditional vector arithmetic method and conditional vector arithmetic unit It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision... | 06/13/2006 |
| 7027446 | Method and apparatus for set intersection rule matching A method and apparatus for of high-speed and memory efficient rule matching, the rule matching being performed on an m-dimensional universe with each dimension bound by a given range of coordinate values, and a set of rules that apply to an undetermined number of co... | 04/11/2006 |
| 7028091 | Web server in-kernel interface to data transport system and cache manager A HTTP request is sent to a web server. A HTTP request including HTTP request data is received. A connection identifier is associated with the HTTP request. The receiving and associating steps are repeated for one or more HTTP requests. The connection identifier and... | 04/11/2006 |
| 6970959 | Multi-execute system calls A computer system may include one or more hosts and a plurality of data storage devices for providing multihop system calls. The data storage devices are interconnected and also connected to the one or more hosts. The connections may be direct or indirect. Each data... | 11/29/2005 |
| 6970988 | Algorithm mapping, specialized instructions and architecture features for smart memory computing A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many exe... | 11/29/2005 |
| 6958718 | Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result ... | 10/25/2005 |
| 6954841 | Viterbi decoding for SIMD vector processors with indirect vector element access A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) ... | 10/11/2005 |
| 6934761 | User level web server cache control of in-kernel http cache Methods and apparatus for managing a HTTP cache in a web server. A HTTP daemon in a web server may provide response data as well as one or more cache control indicators to a cache manager. The cache control indicators are adapted for managing information that is sto... | 08/23/2005 |
| 6931511 | Parallel vector table look-up with replicated index element vector Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector of indices includes: generating a second vector of indices in a vector... | 08/16/2005 |
| 6922716 | Method and apparatus for vector processing A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a... | 07/26/2005 |
| 6904510 | Data processor having a respective multiplexer for each particular field A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is controlled by condition data for a particular field, preferably from an ... | 06/07/2005 |
| 6782468 | Shared memory type vector processing system, including a bus for transferring a vector processing instruction, and control method thereof A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the respective CPUs are grouped into a master CPU which issues a vector proces... | 08/24/2004 |
| 6560775 | Branch preparation A method and system for preparing branch instruction of a computer program, for compiling and execution in a computer system, in which each transfer instruction is split into two instructions: a control transfer preparation instruction and a control trans... | 05/06/2003 |
| 6504495 | Clipping data values in a data processing system A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N-1 (from unclipped numbers in a range of -0.5N to (1.5N-1)), where N is 2m and m is the bit length of the desired clipped and quantized number.... | 01/07/2003 |
| 6446193 | Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, h... | 09/03/2002 |
| 6401194 | Execution unit for processing a data stream independently and in parallel A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more comp... | 06/04/2002 |
| 6336154 | Method of operating a computer system by identifying source code computational elements in main memory A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for b... | 01/01/2002 |
| 6327668 | Determinism in a multiprocessor computer system and monitor and processor therefor A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from t... | 12/04/2001 |
| 6324638 | Processor having vector processing capability and method for executing a vector instruction in a processor A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a... | 11/27/2001 |
| 6314471 | Techniques for an interrupt free operating system A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, t... | 11/06/2001 |
